Parallel signal processing system and method
OwnerWai Wuinventor
Life of this patent
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Abstract
A system and method for processing a plurality of channels, for example audio channels, in parallel is provided. For example, a plurality of telephony channels are processed in order to detect and respond to call progress tones. The channels may be processed according to a common transform algorithm. Advantageously, a massively parallel architecture is employed, in which operations on many channels are synchronized, to achieve a high efficiency parallel processing environment. The parallel processor may be situated on a data bus, separate from a main general-purpose processor, or integrated with the processor in a common board or integrated device. All, or a portion of a speech processing algorithm may also be performed in a massively parallel manner.
Claims20
A parallel signal processing system, comprising:
- at least one central processing unit configured to receive a plurality of data streams in parallel;
- at least one single instruction multiple data processor having a plurality of arithmetic logic units each adapted to operate on a data element, and an instruction decoder, wherein common instructions comprising at least one arithmetic matrix operation and decoded by the instruction decoder, are concurrently executed on data elements of the plurality of data streams in parallel by the plurality of arithmetic logic units;
- and
- a memory accessible by the at least one central processing unit and the at last one single instruction-multiple data processor, configured to buffer communications between the at least one central processing unit and the at least one single instruction multiple data processor.
A parallel signal processing method, comprising:
- receiving a plurality of data streams in parallel by at least one central processing unit;
- concurrently executing common instructions comprising at least one arithmetic matrix operation on the plurality of data streams with respective arithmetic logic units of at least one single instruction multiple data processor, the common instructions being decoded by an instruction decoder;
- and
- accessing a memory by the at least one central processing unit and the at last one single instruction-multiple data processor, to buffer communications between the at least one central processing unit and the at least one single instruction multiple data processor.
A non-transitory computer readable medium storing therein instructions for performing a parallel signal processing method, comprising:
- instructions for receiving a plurality of data streams in parallel by at least one central processing unit;
- instructions for concurrently executing common instructions comprising at least one arithmetic matrix operation on the plurality of data streams with respective arithmetic logic units of at least one single instruction multiple data processor, the common instructions being decoded by an instruction decoder;
- and
- instructions for accessing a memory by the at least one central processing unit and the at last one single instruction-multiple data processor, to buffer communications between the at least one central processing unit and the at least one single instruction multiple data processor.
Dependencies are inferred from the claim text.