Integrated circuit having state machine-driven flops in wrapper chains for device testing
AssigneeJuniper Networks, Inc.
InventorGustav Laub, III
Life of this patent
Estimating the term…
Abstract
Integrated circuits are described that utilize internal state machine-driven logic elements (e.g., flops) within input and/or output wrapper chains that are used to test internal core logic of the integrate circuit. One or more individual logic elements of the wrapper chains within the integrated circuit is implemented as a multi-flop state machine rather than a single digital flip-flop. As multi-flop state machines, each enhanced logic element of a wrapper chain is individually configurable to output pre-selected values so as to disassociate the state machine-driven flops from signal transmission delays that may occur in the input or output wrapper chains of the integrated circuit.
Claims20
An integrated circuit (IC) comprising:
- a core logic having functional logic elements;
- a wrapper chain having a plurality of flops for testing the core logic, wherein the plurality of flops of the wrapper chain are sequentially interconnected along a scan path for shifting scan data through successive ones of the flops during testing of the core logic;
- and
- at least one state machine-driven flop connected along the scan path of the wrapper chain,
- wherein the state machine-driven flop is individually configurable, during the testing, to output to the core logic a first value independent from the scan data being shifted along the scan path and received by the state machine-driven flop, and
- wherein at least one flop of the plurality of flops is set to output to the core logic a second value that is equal to the scan data being shifted along the scan path and received by the at least one flop.
A system comprising:
- a tester;
- and
- an integrated circuit (IC) comprising:
- a core logic having functional logic elements;
- an input wrapper chain having a plurality of flops for testing the core logic, wherein the plurality of flops of the wrapper chain are sequentially interconnected along a scan path for shifting scan data through successive ones of the flops during testing of the core logic;
- an output wrapper chain;
- and
- at least one state machine-driven flop connected along the scan path of the input wrapper chain, wherein the state machine-driven flop is individually configurable, during the testing, to output a value independent from the scan data being shifted along the scan path and received by the state machine-driven flop;
- wherein the input wrapper chain is configured to:
- load, during a load phase responsive to receiving a set of load phase clock signals at a slow clock frequency, an input string of data from the tester so as to load values into the plurality of flops and configure the state machine-driven flop to output the value independent from the scan data being shifted along the scan path;
- wherein the output wrapper chain is configured to:
- capture, during a capture phase responsive to receiving a set of capture phase clock signals at a fast clock frequency, a captured string of data from a plurality of functional paths through the core logic;
- and
- unload, during an unload phase responsive to receiving a set of unload phase clock signals at the slow clock frequency, the captured string of data to the tester.
Dependencies are inferred from the claim text.