Detection circuit, corresponding device and method

An electronic device comprising:

• a radio-frequency antenna;
• an edge detection circuit comprising an input with a first node and an output with an output node, the radio-frequency antenna being coupled to the first node, the radio-frequency antenna configured to receive an analog signal that is an amplitude modulated radio-frequency signal for a digital signal;
• the output node being configured to provide an output signal indicative of rising and falling edges of an envelope of the analog signal, the rising and falling edges being indicative of rising and falling edges of the digital signal;
• and
• a first current path between a power supply node and the first node, the first current path comprising a first transistor coupled between the first node and a first bias source, the first bias source coupled between the first transistor and the power supply node, wherein:
• the output node is coupled to a first intermediate node in the first current path between the transistor and the first bias source, and
• a control terminal of the first transistor is coupled to the output node via a feedback network.

A method of operating an electronic device, the method comprising:

• receiving, at a first node of an edge detection circuit, an analog signal that is an amplitude modulated radio-frequency signal for a digital signal;
• having a current flow in a first current path between a power supply node and the first node, the first current path comprising a first transistor coupled between the first node and a first bias source, the first bias source coupled between the first transistor and the power supply node,
• operating the first transistor in sub-threshold regime in which a current flowing through the first transistor is exponentially dependent on a gate-source voltage applied to the first transistor;
• and
• reading, at an output node of the edge detection circuit, an output signal indicative of rising and falling edges of an envelope of the analog signal, wherein the output node is coupled to a first intermediate node in the first current path between the transistor and the first bias source, and wherein a control terminal of the first transistor is coupled to the output node via a feedback network.