Selective liner on backside via and method thereof

A method, comprising:

• providing a structure having a substrate, a semiconductor fin over the substrate, two source/drain (S/D) features over the semiconductor fin, an isolation structure on sidewalls of the semiconductor fin, a dielectric capping layer over the semiconductor fin, one or more channel semiconductor layers over the dielectric capping layer, and a gate structure engaging the one or more channel semiconductor layers;
• thinning down the substrate until the semiconductor fin is exposed;
• selectively etching the semiconductor fin to form a trench, wherein the trench exposes surfaces of the two S/D features, a surface of the dielectric capping layer, and sidewalls of the isolation structure;
• forming a silicide feature on the surfaces of the S/D features;
• depositing an inhibitor on the silicide feature but not on the surface of the dielectric capping layer and the sidewalls of the isolation structure;
• depositing a dielectric liner layer on the sidewalls of the isolation structure and the surface of the dielectric capping layer but not on the inhibitor;
• selectively removing the inhibitor;
• and
• forming a via structure in the trench.

A method, comprising:

• providing a structure having a substrate, a semiconductor fin over the substrate, two source/drain (S/D) regions over the semiconductor fin, a first dielectric layer over the semiconductor fin, an isolation structure adjacent to sidewalls of the semiconductor fin, one or more channel semiconductor layers over the first dielectric layer and connecting the two S/D regions, and a gate structure wrapping around the one or more channel semiconductor layers, wherein the gate structure is disposed at a frontside of the structure;
• thinning down the structure from a backside of the structure opposite to the frontside of the structure until the semiconductor fin is exposed from the backside of the structure;
• selectively etching the semiconductor fin to form a trench, wherein the trench exposes surfaces of the two S/D regions, the first dielectric layer, and the isolation structure;
• forming a silicide feature on the surfaces of the S/D regions;
• selectively depositing an inhibitor in the trench and on the silicide feature but not on the surfaces of the first dielectric layer and the isolation structure;
• selectively depositing a dielectric liner layer in the trench and on the surfaces of the isolation structure and the first dielectric layer but not on the surfaces of the inhibitor;
• selectively removing the inhibitor;
• depositing a dielectric layer to fill the trench;
• etching the dielectric layer to form a via hole, the via hole exposing the silicide feature on one of the two S/D regions;
• and
• forming a via structure in the via hole.