Self-aligned etch in semiconductor devices

A semiconductor device comprising:

• a first transistor structure comprising a first nanostructure, a first gate structure surrounding the first nanostructure, and a first source/drain region adjacent the first gate structure;
• a first interconnect structure on a front-side of the first transistor structure;
• and
• a second interconnect structure on a backside of the first transistor structure, the second interconnect structure comprising:
• a first dielectric layer on the backside of the first transistor structure;
• and
• a first spacer extending through the first dielectric layer, a first sidewall of the first spacer being aligned with a first end surface of the first gate structure;
• and
• an air gap between the first end surface of the first gate structure and a second end surface of a second gate structure, wherein a longitudinal axis of the second gate structure is aligned with a longitudinal axis of the first gate structure.

A method comprising:

• forming a transistor structure on a semiconductor substrate;
• thinning the semiconductor substrate to expose a fin;
• after thinning the semiconductor substrate, forming first spacers along sidewalls of the fin;
• etching a source/drain region of the transistor structure using the first spacers as a mask;
• and
• forming a first interlayer dielectric adjacent the source/drain region.