Data processing apparatus, and data processing method

A data processing method for a data processing apparatus including frequency interleaver circuitry that includes memory configured to store data, and address generator circuitry configured to produce a write address and a read address, the frequency interleaver circuitry being configured to write the data to the memory in accordance with the write address and to read out the data from the memory in accordance with the read address, thereby carrying out frequency interleaving, the method comprising:

• generating a first pseudo random bit stream;
• generating a second pseudo random bit stream;
• alternately producing a bit as 0 and as 1 as an additional bit added as a most significant bit of the first pseudo random bit stream;
• and
• producing the write address or the read address by obtaining an exclusive-OR between the first pseudo random bit stream having the additional bit added as the most significant bit and the second pseudo random bit stream.

A data processing apparatus comprising:

• frequency deinterleaver circuitry that includes memory configured to store data, and address generator circuitry configured to produce a write address and a read address, the frequency deinterleaver circuitry being configured to write the data to the memory in accordance with the write address and to read out the data from the memory in accordance with the read address, thereby carrying out frequency deinterleaving,
• wherein the address generator circuitry is configured to:
• produce a first pseudo random bit stream,
• produce a second pseudo random bit stream,
• alternately produce a bit as 0 and as 1 as an additional bit added as a most significant bit of the first pseudo random bit stream, and
• produce the write address or the read address by obtaining an exclusive-OR between the first pseudo random bit stream having the additional bit added as the most significant bit and the second pseudo random bit stream.

A data processing method for a data processing apparatus including frequency deinterleaver circuitry that includes memory configured to store data, and address generator circuitry configured to produce a write address and a read address, the frequency deinterleaver circuitry being configured to write the data to the memory in accordance with the write address and to read out the data from the memory in accordance with the read address, thereby carrying out frequency deinterleaving, the method comprising:

• generating a first pseudo random bit stream;
• generating a second pseudo random bit stream;
• alternately producing a bit as 0 and as 1 as an additional bit added as a most significant bit of the first pseudo random bit stream;
• and
• producing the write address or the read address by obtaining an exclusive-OR between the first pseudo random bit stream having the additional bit added as the most significant bit and the second pseudo random bit stream.