Hybrid analog-to-digital converter with inverter-based residue amplifier
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMartin Kinyua, Eric Soenen
Life of this patent
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Abstract
An apparatus and method for analog to digital conversion of analog input signals are disclosed herein. In some embodiments, an analog-to-digital (ADC) may comprise: a first successive approximation register (SAR) circuit comprising a fast SAR (FSAR) circuit and a residue digital-to-analog converter (RDAC) circuit and a residue amplifier circuit, coupled to the RDAC circuit, comprising an amplifier circuit that is configured to amplify a residual signal generated by the RDAC circuit, wherein the amplifier circuit comprises a deadzone control circuit and a first, second and third inverter stages, wherein the third stage is biased to operate in a sub-threshold region.
Claims20
An analog-to-digital converter (ADC) circuit, comprising:
- a first successive approximation register (SAR) circuit comprising a fast SAR (FSAR) circuit and a residue digital-to-analog converter (RDAC) circuit,
- wherein the FSAR circuit and the RDAC circuit are configured to concurrently receive an analog input signal thereby decoupling a first high-speed signal path through the FSAR circuit from a second slow-speed noise-limited signal path through the RDAC circuit;
- and
- a residue amplifier circuit, coupled to the RDAC circuit, comprising an amplifier circuit that is configured to amplify a residual signal generated by the RDAC circuit,
- wherein the amplifier circuit comprises a deadzone control circuit and a first, second and third inverter stages, wherein the third stage is biased to operate in a sub-threshold region through the deadzone control circuit that is configured to generate a bias current.
A residual amplifier, comprising:
- a first inverter stage configured to receive a residual signal from a residue digital-to-analog converter (RDAC) circuit of a first successive approximation register (SAR) circuit;
- a second inverter stage, coupled to the first inverter stage, comprising a first NMOS and PMOS transistors connected between a voltage supply and ground and a resistor coupled between the first NMOS and PMOS transistors at their respective drains;
- a third inverter stage, coupled to the second inverter stage, comprising a second NMOS and PMOS transistors connected between a voltage supply and ground and configured to generate an output signal that is an amplified version of the received residual signal and biased to operate in a sub-threshold region;
- and
- a deadzone control circuit, coupled to gates of the second NMOS and PMOS transistors, comprising a differential amplifier with an active load configured to receive a reference voltage at one of its inputs and a plurality of current mirrors couple to an output of the differential amplifier,
- wherein deadzone control circuit is configured to generate a bias current for biasing the second NMOS and PMOS transistors in the third inverter stage to operate in the sub-threshold region.
A method for amplifying a residue signal received at a residue amplifier from a residue digital-to-analog converter (RDAC) circuit of a first successive approximation register (SAR) circuit, the method comprising:
- enabling a differential amplifier when, in an amplification phase, the RDAC circuit is configured to hold the residual signal;
- receiving a reference voltage at a first differential input of the differential amplifier,
- generating a bias current through a plurality of current mirrors controlled by the reference voltage, wherein gate terminals of the plurality of current mirrors are coupled to an output of the differential amplifier and drain terminals of the plurality of current mirrors are coupled to gate terminals of transistors located in an output stage of the residue amplifier;
- and
- biasing, through the bias current, the gate terminals of the transistors located in the output stage of the residue amplifier to operate in a sub-threshold region.
Dependencies are inferred from the claim text.