Digital filter structure

An audio signal processing structure arranged to receive one or more clocked input signals having a first clock rate, and which is driven at a second clock rate higher than said first clock rate;

• said audio signal processing structure comprising a plurality of delay elements and multiplexing circuitry arranged to selectively engage the delay elements such that, at every clock cycle of said audio signal processing structure, a filter operation is performed on a different stream of data;
• and the multiplexing circuitry comprising a demultiplexer and a multiplexer, wherein the demultiplexer and the multiplexer are coupled to the plurality of delay elements;
• and wherein the demultiplexer, the multiplexer and the plurality of delay elements are provided on a feedback loop;
• the audio signal processing structure further comprising a coefficient multiplexer arranged to select between a plurality of filter coefficients.

Headphones comprising an audio signal processing structure, wherein the audio signal processing structure is arranged to receive one or more clocked input signals having a first clock rate, and which is driven at a second clock rate higher than said first clock rate;

• said audio signal processing structure comprising a plurality of delay elements and multiplexing circuitry arranged to selectively engage the delay elements such that, at every clock cycle of said audio signal processing structure, a filter operation is performed on a different stream of data;
• and the multiplexing circuitry comprising a demultiplexer and a multiplexer, wherein the demultiplexer and the multiplexer are coupled to the plurality of delay elements;
• and wherein the demultiplexer, the multiplexer and the plurality of delay elements are provided on a feedback loop;
• the audio signal processing structure further comprising a coefficient multiplexer arranged to select between a plurality of filter coefficients.

A method of digital filtering comprising:

• providing a digital filter structure arranged to receive one or more clocked input signals having a first clock rate, and which is driven at a second clock rate higher than said first clock rate;
• said digital filter structure comprising a plurality of delay elements and multiplexing circuitry arranged to selectively engage the delay elements such that, at every clock cycle of said digital filter structure, a filter operation is performed on a different stream of data;
• and
• the multiplexing circuitry comprising a demultiplexer and a multiplexer, wherein the demultiplexer and the multiplexer are coupled to the plurality of delay elements;
• and wherein the demultiplexer, the multiplexer and the plurality of delay elements are provided on a feedback loops,
• the digital filter structure further comprising a coefficient multiplexer arranged to select between a plurality of filter coefficients.