Transistor bias adjustment for optimization of third order intercept point in a cascode amplifier

A method for optimizing a third order intercept point (IP3) in a multi-gain-state amplifier comprising at least a low gain-state and a high gain-state, the method comprising:

• during operation in the low-gain state, biasing cascode transistors of the multi-gain-state amplifier for an optimized value of the IP3;
• during operation in the high-gain state, biasing cascode transistors of the multi-gain-state amplifier for an optimized value of the IP3;
• wherein the optimized value of the IP3 during operation in the high-gain state is obtained by providing a drain-to-source voltage of an output transistor that is higher than a drain-to-source voltage of the output transistor during operation in the low gain-state,
• wherein the optimized value of the IP3 during operation in the low gain-state is obtained by providing a drain-to-source voltage of an input transistor that is higher than a drain-to-source voltage of the input transistor during operation in the high gain-state, and
• wherein the multi-gain-state amplifier comprises a low noise amplifier (LNA) comprising a stack of a plurality of series connected transistors comprising the input transistor and one or more cascode transistors comprising the output transistor, the stack coupled between a substantially fixed supply voltage and a reference ground.

A multi-gain-state amplifier circuit for operation according to at least a low gain-state and a high gain-state, the multi-gain-state amplifier circuit comprising:

• i) a low noise amplifier (LNA) comprising:
• a stack of a plurality of series connected transistors comprising an input transistor and one or more cascode transistors comprising an output transistor, the stack coupled between a substantially fixed supply voltage and a reference ground;
• and
• ii) a gain decoder and bias control circuit that is configured to selectively generate biasing voltages to gates of the one or more cascode transistors for operation according to the low gain-state and the high gain-state,
• wherein during operation in the high gain-state, the biasing voltages are configured to provide a drain-to-source voltage of the output transistor that is higher than a drain-to-source voltage of the output transistor during operation in the low gain-state,
• wherein the gain decoder and bias control circuit selectively generates the biasing voltages based on an input control signal that is one of:
• a) a digital signal, b) an analog signal, or c) a combination of a) and b), and
• wherein the gain decoder and bias control circuit comprises:
• a gain decoder circuit that decodes the input control signal into a target gain-state comprising the low gain-state or the high gain-state;
• and
• a bias control circuit that generates the biasing voltages based on the target gain-state, the bias control circuit comprising one or more of:
• p) an analog-to-digital conversion circuit, q) a digital-to-analog conversion circuit, r) a digital circuit, s) an analog circuit, or t) a memory circuit.