Semiconductor device with fish bone structure and methods of forming the same

A semiconductor device comprising:

• first semiconductor stacks over a first region of a substrate, second semiconductor stacks over a second region of the substrate, wherein each of the first and second semiconductor stacks includes semiconductor layers stacked up and separated from each other;
• a first dummy spacer between the first semiconductor stacks and a second dummy spacer between the second semiconductor stacks, wherein the first dummy spacer contacts sidewalls of the semiconductor layers of the first semiconductor stacks, and the second dummy spacer contacts sidewalls of the semiconductor layers of the second semiconductor stacks;
• and
• a first gate structure wrapping each semiconductor layer of the first semiconductor stacks and a second gate structure wrapping each semiconductor layer of the second semiconductor stacks, wherein a top portion of the first gate structure is separated by the first dummy spacer and a top portion of the second gate structure extends continuously over a top surface of the second dummy spacer.

A method of forming a semiconductor device, comprising:

• forming a first semiconductor stack and a second semiconductor stack over a substrate, wherein each of the first and second semiconductor stack includes first semiconductor layers and second semiconductor layers including different materials and are alternately stacked up;
• forming a first dummy spacer and a second dummy spacer, the first dummy spacer comprising a first channel region in contact with a first sidewall of the first and second semiconductor layers of the first semiconductor stack and a first source/drain region adjacent the first channel region, the second dummy spacer comprising a second channel region in contact with a second sidewall of the first and second semiconductor layers of the second semiconductor stack and a second source/drain region adjacent the second channel region;
• after the forming of the first dummy spacer and the second dummy spacer, depositing a dummy dielectric layer over the first semiconductor stack, the second semiconductor stack, the first dummy spacer, and the second dummy spacer;
• depositing a dielectric layer over the first source/drain region and the second source/drain region;
• selectively removing the second semiconductor layers of the first and second semiconductor stacks;
• removing the dummy dielectric layer;
• selectively etching back the second channel region while the first source/drain region and the second source/drain region are covered by the dielectric layer;
• and
• after the selectively etching back, forming a metal gate structure wrapping around each of the first semiconductor layers of the first and second semiconductor stacks.