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US 11,323,131 B2Granted
Delay-based spread spectrum clock generator circuit
AssigneeSTMicroelectronics International N.V.
InventorsGagan Midha, Kallol Chatterjee
Life of this patent
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Abstract
A delay chain circuit with series coupled delay elements receives a reference clock signal and outputs phase-shifted clock signals. A multiplexer circuit receives the phase-shifted clock signals and selects among the phase-shifted clock signals for output as in response to a selection signal. The selection signal is generated by a control circuit from a periodic signal having a triangular wave profile. A sigma-delta modulator converts the periodic signal to a digital signal, and an integrator circuit integrates the digital signal to output the selection signal. The selected phase-shifted clock signal is applied as the reference signal to a phase locked loop which generates a spread spectrum clock signal.
Claims70
A circuit, comprising:
- a delay chain circuit having an input configured to receive a reference clock signal, the delay chain circuit including a plurality of delay elements coupled in series, wherein the delay chain circuit outputs a plurality of phase-shifted clock signals;
- a first multiplexer circuit having inputs coupled to receive the plurality of phase-shifted clock signals and having a first selection input configured to receive a first selection signal which selects one of the plurality of phase-shifted clock signals for output;
- and
- a control circuit configured to generate values for the first selection signal from a waveform signal having a periodic triangular wave profile, wherein the control circuit includes:
- a sigma-delta modulator configured to convert the waveform signal to generate a modulated digital signal from which the values for the first selection signal are generated;
- and
- a register circuit configured to latch the first selection signal in response to a control clock, wherein the control clock is a delayed version of the phase-shifted clock signal selected by the first selection signal and output by the first multiplexer circuit.
4 more elements
A circuit, comprising:
- a delay chain circuit having an input configured to receive a reference clock signal, the delay chain circuit including a plurality of delay elements coupled in series, wherein the delay chain circuit outputs a plurality of phase-shifted clock signals;
- a first multiplexer circuit having inputs coupled to receive the plurality of phase-shifted clock signals and having a first selection input configured to receive a first selection signal which selects one of the plurality of phase-shifted clock signals for output
- a control circuit configured to generate values for the first selection signal from a waveform signal having a periodic triangular wave profile, wherein the control circuit includes:
- a sigma-delta modulator configured to convert the waveform signal to generate a modulated digital signal from which the values for the first selection signal are generated;
- and
- a register circuit configured to latch the first selection signal in response to a control clock, wherein the control clock is a further selected one of the plurality of phase-shifted clock signals.
3 more elements
A method, comprising:
- selecting one of a plurality of phase-shifted clock signals for output in response to a selection signal;
- generating values for the selection signal by performing sigma-delta modulation of a waveform signal having a periodic triangular wave profile;
- processing the selecting one of the plurality of phase-shifted clock signals to output a spread spectrum clock signal;
- and
- latching the value of the selection signal in response to a control clock, wherein the control clock is a delayed version of the selected one of the phase-shifted clock signals.
2 more elements
A method, comprising,
- selecting one of a plurality of phase-shifted clock signals for output in response to a selection signal;
- generating values for the selection signal by performing sigma-delta modulation of a waveform signal having a periodic triangular wave profile;
- processing the selecting one of the plurality of phase-shifted clock signals to output a spread spectrum clock signal;
- and
- latching the value of the selection signal in response to a control clock, wherein the control clock is a further selected one of the plurality of phase-shifted clock signals.
2 more elements
A circuit, comprising:
- a delay chain circuit having an input configured to receive a reference clock signal, the delay chain circuit including a plurality of delay elements coupled in series, wherein the delay chain circuit outputs a plurality of phase-shifted clock signals;
- a first multiplexer circuit having inputs coupled to receive the plurality of phase-shifted clock signals and having a first selection input configured to receive a first selection signal which selects one of the plurality of phase-shifted clock signals for output;
- and
- a control circuit configured to generate values for the first selection signal from a waveform signal having a periodic triangular wave profile, wherein the control circuit includes:
- a sigma-delta modulator configured to convert the waveform signal to generate a modulated digital signal from which the values for the first selection signal are generated;
- a compensation circuit configured to determine a number of delay elements within the delay chain circuit which change state in response to one cycle of the reference clock signal;
- and
- wherein the control circuit adjusts a modulation depth of the waveform signal having the triangular wave profile in response to the determined number of delay elements.
5 more elements
A circuit, comprising:
- a delay chain circuit having an input configured to receive a reference clock signal, the delay chain circuit including a plurality of delay elements coupled in series, wherein the delay chain circuit outputs a plurality of phase-shifted clock signals;
- a first multiplexer circuit having inputs coupled to receive the plurality of phase-shifted clock signals and having a first selection input configured to receive a first selection signal which selects one of the plurality of phase-shifted clock signals for output;
- and
- a control circuit configured to generate values for the first selection signal from a waveform signal having a periodic triangular wave profile, wherein the control circuit includes:
- a sigma-delta modulator configured to convert the waveform signal to generate a modulated digital signal from which the values for the first selection signal are generated;
- a compensation circuit configured to determine a number of delay elements within the delay chain circuit which change state in response to one cycle of the reference clock signal;
- and
- wherein the control circuit adjusts a number of quantization levels for the sigma-delta modulator in response to the determined number of delay elements.
5 more elements
A circuit, comprising:
- a delay chain circuit having an input configured to receive a reference clock signal, the delay chain circuit including a plurality of delay elements coupled in series, wherein the delay chain circuit outputs a plurality of phase-shifted clock signals;
- a first multiplexer circuit having inputs coupled to receive the plurality of phase-shifted clock signals and having a first selection input configured to receive a first selection signal which selects one of the plurality of phase-shifted clock signals for output;
- and
- a control circuit configured to generate values for the first selection signal from a waveform signal having a periodic triangular wave profile, wherein the triangular wave profile is defined by a modulation frequency and a modulation depth;
- wherein the control circuit includes:
- a sigma-delta modulator configured to convert the waveform signal to generate a modulated digital signal from which the values for the first selection signal are generated;
- and
- wherein the modulation depth is scaled by a compensation value to account for process and voltage variation of the plurality of delay elements.
5 more elements
A method, comprising:
- selecting one of a plurality of phase-shifted clock signals for output in response to a selection signal;
- generating values for the selection signal by performing sigma-delta modulation of a waveform signal having a periodic triangular wave profile;
- processing the selecting one of the plurality of phase-shifted clock signals to output a spread spectrum clock signal;
- determining a number of delay elements within a delay chain circuit generating the plurality of phase-shifted clock signals from a reference clock signal which change state in response to one cycle of the reference clock signal;
- and
- adjusting a modulation depth of the waveform signal having the triangular wave profile in response to the determined number of delay elements.
3 more elements
A method, comprising:
- selecting one of a plurality of phase-shifted clock signals for output in response to a selection signal;
- generating values for the selection signal by performing sigma-delta modulation of a waveform signal having a periodic triangular wave profile;
- processing the selecting one of the plurality of phase-shifted clock signals to output a spread spectrum clock signal;
- determining a number of delay elements within a delay chain circuit generating the plurality of phase-shifted clock signals from a reference clock signal which change state in response to one cycle of the reference clock signal;
- and
- adjusting a number of quantization levels for the sigma-delta modulation in response to the determined number of delay elements.
3 more elements
A method, comprising:
- selecting one of a plurality of phase-shifted clock signals for output in response to a selection signal;
- generating values for the selection signal by performing sigma-delta modulation of a waveform signal having a periodic triangular wave profile;
- processing the selecting one of the plurality of phase-shifted clock signals to output a spread spectrum clock signal;
- and
- scaling a modulation depth of the waveform signal by a compensation value to account for process and voltage variation of delay elements within a delay chain circuit generating the plurality of phase-shifted clock signals.
2 more elements
A method, comprising:
- selecting one of a plurality of phase-shifted clock signals for output in response to a selection signal;
- generating values for the selection signal by performing sigma-delta modulation of a waveform signal having a periodic triangular wave profile;
- processing the selecting one of the plurality of phase-shifted clock signals to output a spread spectrum clock signal;
- and
- adjusting a number of quantization levels for the sigma-delta modulation to account for said process and voltage variation of delay elements within the delay chain circuit.
2 more elements
Dependencies are inferred from the claim text.