High-speed multiplexer

A method comprising:

• receiving a set of differential input signals at an input stage of a multiplexer;
• generating, at a differential output node of the multiplexer, a differential output signal based on the set of differential input signals;
• equalizing the differential output signal by driving an active inductive load pair using the differential output signal, the equalizing of the differential output signal resulting in an equalized differential output signal, the active inductive load pair comprising:
• a first active inductive load connected to a first output node of the differential output node pair;
• a second active inductive load connected to a second output node of the differential output node pair;
• and
• a first bias control element and a second bias control element, the first bias control element and the second bias control element receiving a first bias voltage at a common gate node, the first bias control element being connected to a first drain node, the second bias control element being connected to a second drain node, the first drain node being connected to a drain of a first p-channel field-effect transistor (pFET) device of the first active inductive load, the second drain node being connected to a drain of a second pFET device of the second active inductive load;
• and
• providing the equalized differential output signal at the differential output node of the multiplexer.

A system comprising:

• a driver;
• and
• a multiplexer comprising a differential output node connected to a driver input of the driver, the multiplexer further comprising:
• a set of differential input pairs to receive a set of differential input signals and provide a differential output signal based on the set of differential input signals at the differential output node pair;
• an active inductive load pair connected to the set of differential input pairs, the active inductive load pair equalizing the differential output signal provided at the differential output node pair, the active inductive load pair comprising a first active inductive load crossed-coupled with a second active inductive load by a first cross-coupling capacitor and a second cross-coupling capacitor;
• and
• a first bias control element and a second bias control element, the first bias control element and the second bias control element receiving a first bias voltage at a common gate node, the first bias control element being connected to a first drain node, the second bias control element being connected to a second drain node, the first drain node being connected to a drain of a first p-channel field-effect transistor (pFET) device of the first active inductive load, the second drain node being connected to a drain of a second pFET device of the second active inductive load.