Self-referenced clockless delay adaptation for random data

An apparatus, comprising:

• a first delay line coupled to an input;
• a second delay line coupled to an output of the first delay line;
• an XNOR gate coupled to the input and the output of the first delay line;
• and
• an OR gate coupled to the input and the output of the first delay line;
• and
• a controller coupled to an output of the XNOR gate and an output of the OR gate, wherein the controller is further coupled to at least one of the first and second delay lines.

A delay adaptation loop, comprising:

• a first delay line;
• a second delay line;
• a first autocorrelation calculator configured to apply a first autocorrelation function to input data and output data of at least one of the first and second delay lines, resulting in a first autocorrelation;
• a second autocorrelation calculator configured to apply a second autocorrelation function to the input data and the output data of the at least one of the first and second delay lines, resulting in a second autocorrelation;
• and
• a controller coupled to the first and second autocorrelation calculators and to at least one of the first and second delay lines, wherein the controller is configured to generate a control signal for the at least one of the first and second delay lines based on the first and second autocorrelations.

An apparatus, comprising:

• a voltage-to-current (V-I) converter configured to receive a control voltage Vctrl and generate a control current Ictrl;
• and
• a differential amplifier configured to delay an input signal based on Vctrl and Ictrl;
• wherein the V-I converter comprises:
• an operational amplifier (op-amp) comprising a positive input, a negative input configured to receive Vctrl, and an output;
• a first transistor comprising a first control terminal coupled to the output of the op-amp, a first current terminal coupled to the positive input of the op-amp, and a second current terminal coupled to ground;
• a first resistor coupled to a supply voltage rail and to the positive input of the op-amp and the first current terminal of the first transistor;
• a second transistor comprising a second control terminal coupled to the output of the op-amp, a third current terminal, and a fourth current terminal coupled to ground;
• a current source coupled to the third current terminal;
• a third transistor comprising a fifth current terminal, a sixth current terminal, and a third control terminal coupled to the current source and the third current terminal, wherein the fifth current terminal is coupled to the third control terminal, the current source, and the third current terminal;
• and
• a second resistor coupled to the sixth current terminal and to ground.