Statistical mode determination

A method of operating an apparatus comprising:

• receiving, by input circuitry, input data comprising at least one data element;
• generating, by shift circuitry, for each data element of the input data, a bit-map giving a one-hot encoding representation of the data element, wherein a position of a set bit in the bit-map is dependent on the data element;
• generating, by summation circuitry, a position summation value for each position in the bit-map, wherein each position summation value is a sum across all bit-maps generated from the input data;
• determining, by maximum identification circuitry, at least one largest position summation value generated;
• and
• generating, by output circuitry, an indication of at least one data element corresponding to the at least one largest position summation value.

A non-transitory storage medium storing a computer program that when executed controls a host data processing apparatus to provide an instruction execution environment comprising:

• data processing logic to perform data processing operations, the data processing logic comprising:
• input logic to receive input data comprising at least one data element;
• shift logic to generate, for each data element of the input data, a bit-map giving a one-hot encoding representation of the data element, wherein a position of a set bit in the bit-map is dependent on the data element;
• summation logic to generate a position summation value for each position in the bit-map, wherein each position summation value is a sum across all bit-maps generated by the shift logic from the input data;
• maximum identification logic to determine at least one largest position summation value generated by the summation logic;
• and
• output logic to generate an indication of at least one data element corresponding to the at least one largest position summation value,
• instruction decoder logic to decode instructions and to generate control signals in dependence on the instructions to control the data processing logic to perform the data processing operations,
• wherein the instruction decoder logic is responsive to a statistical mode instruction specifying a vector input register to generate control signals to control the input logic to receive the input data from the vector input register.