Encoding method and device, decoding method and device, and storage medium

A decoding method comprising:

• decoding a target bit sequence having a code rate R2 with a low density parity check code LDPC having a code rate R1, to obtain an initial bit sequence to be encoded, where 0≤R2≤R1≤1, wherein the target bit sequence is formed by cascading a first bit sequence and a second bit sequence, the first bit sequence is obtained by encoding an initial bit sequence to be encoded with a LDPC having a code rate R1, and the second bit sequence is obtained by dividing the first bit sequence into t bit sequence segments and linearly combining at least two bit sequence segments in the first bit sequence, wherein a relationship exists between the number t of the bit sequence segments and the code rate R1:
• t
• =
• [
• [
• j
• R
• 1
• ]
• ]
• ,
• wherein t is a positive integer greater than or equal to 1, j is a positive integer, and the operator represents a rounding operation;
• and linearly combining at least two bit sequence segments in the first bit sequence comprises:
• a selecting step of selecting t1 bit sequence segments from t bit sequence segments;
• a combining step of linearly combining bits at corresponding positions in the t1 bit sequence segments to obtain a bit sequence segment D1, where 1<t1≤t;
• repeating the selecting step and the combining step to generate w bit sequence segments {D1, D2, . . . , Dw}, where w is a positive integer;
• and cascading the w bit sequence segments to obtain the second bit sequence.

An encoding device, comprising:

• a processor;
• a memory for storing instructions executable by the processor;
• wherein the processor is configured to:
• encode an initial bit sequence to be encoded with a low density parity check code LDPC having a code rate R1, to obtain a first bit sequence, where 0≤R1≤1;
• divide the first bit sequence into t bit sequence segments, wherein a relationship exists between the number t of the bit sequence segments and the code rate R1:
• t
• =
• [
• [
• j
• R
• 1
• ]
• ]
• ,
• where t is a positive integer greater than or equal to 1, j is a positive integer, and the operator represents a rounding operation;
• linearly combine at least two bit sequence segments in the first bit sequence to obtain a second bit sequence, wherein the processor is further configured to:
• select t1 bit sequence segments from t bit sequence segments of the first bit sequence;
• linearly combine bits at corresponding positions in the t1 bit sequence segments to obtain a bit sequence segment D1, where 1<t1≤t;
• and cascade w bit sequence segments {D1, D2, . . . , Dw} generated by the selection unit and the combining unit to obtain the second bit sequence, where w is a positive integer;
• and
• cascade the first bit sequence and the second bit sequence to obtain a target bit sequence having a code rate R2, where 0≤R2≤R1≤1.