Delay based comparator

An analog to digital converter (ADC) comprising:

• a first delay circuit having a first complementary input operable to receive a complementary analog input signal, a second complementary input operable to receive a first complementary reference voltage, and a first complementary signal output comprised of a first signal output and a second signal output that is the complement of the first signal output;
• a second delay circuit having a third complementary input operable to receive the complementary analog input signal, a fourth complementary input operable to receive a second complementary reference voltage that is different than the first complementary reference voltage, and a second complementary signal output;
• a first comparator having an input coupled to the first complementary signal output, the first comparator having a first comparator output;
• a second comparator having an input coupled to the second complementary signal output, the second comparator having a second comparator output;
• a first dummy comparator coupled to the first comparator output;
• a second dummy comparator coupled to the second comparator output;
• a first interpolation comparator having a first interpolation input coupled to the first comparator output and a second interpolation input coupled to the second comparator output;
• and
• wherein a signal at the first signal output precedes or is delayed with respect to a signal at the second signal output responsive to whether the complementary analog input signal is larger than or smaller than the first complementary reference voltage.