Recessed channel structure in FDSOI

An integrated circuit (IC) comprising:

• a semiconductor-on-insulator (SOI) substrate comprising a base substrate, an insulator layer over the base substrate, and a semiconductor device layer over the insulator layer;
• a source region and a drain region disposed in the semiconductor device layer, the source region and the drain region having a first conductivity type;
• a channel region disposed in the semiconductor device layer and separating the source region and the drain region, the channel region having a second conductivity type opposite the first conductivity type, the channel region including a central region, a first peripheral region separating the source region from the central region, and a second peripheral region separating the drain region from the central region, the central region having an upper surface that is recessed relative to an upper surface of the first and second peripheral regions, such that the semiconductor device layer has a first thickness in the central region of the channel region and a second thickness in the first and second peripheral regions of the channel region;
• and
• a sidewall spacer structure disposed over the first and second peripheral regions, wherein a bottom surface of the sidewall spacer structure has outer regions resting on the upper surfaces of the first and second peripheral regions, and the bottom surface of the sidewall spacer structure has overhang regions extending inwardly past the upper surface of the first and second peripheral regions,
• wherein a ratio of first thickness to the second thickness is less than 4:7.

An integrated circuit (IC) comprising:

• a semiconductor-on-insulator (SOI) substrate comprising a base substrate, an insulator layer over the base substrate, and a semiconductor device layer over the insulator layer;
• a source region and a drain region disposed in the semiconductor device layer, the source region and the drain region having a first conductivity type;
• a channel region disposed in the semiconductor device layer and separating the source region and the drain region, the channel region having a second conductivity type opposite the first conductivity type, the channel region including a central region, a first peripheral region separating the source region from the central region, and a second peripheral region separating the drain region from the central region, the central region having an upper surface that is recessed relative to an upper surface of the first and second peripheral regions, such that the semiconductor device layer has a first thickness in the central region of the channel region and a second thickness in the first and second peripheral regions of the channel region, the first thickness being less than the second thickness;
• and
• a sidewall spacer structure disposed over the first and second peripheral regions, wherein a bottom surface of the sidewall spacer structure has outer regions resting on the upper surfaces of the first and second peripheral regions, and the bottom surface of the sidewall spacer structure has overhang regions extending inwardly past the upper surface of the first and second peripheral regions.