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US 11,315,925 B2Granted
Uniform gate width for nanostructure devices
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJui-Chien Huang, Shih-Cheng Chen, Chih-Hao Wang, Kuo-Cheng Chiang, Zhi-Chang Lin, Jung-Hung Chang, Lo-Heng Chang, Shi Ning Ju, Guan-Lin Chen
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Abstract
According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.
Claims20
A semiconductor device comprising:
- a substrate;
- a fin stack comprising:
- a plurality of nanostructures;
- a gate device surrounding each of the nanostructures, a thickness of each gate device differs between different layers of the fin stack;
- inner spacers along the gate device and between the nanostructures, wherein a width of the inner spacers differs between different layers of the fin stack.
2 more elements
A semiconductor device comprising:
- a substrate;
- a transistor device comprising:
- two source/drain regions;
- a fin stack having a plurality of channel features extending between the two source/drain regions;
- a gate feature surrounding the plurality of channel features so as to include a plurality of gate regions between each of the channel features;
- and
- sidewall spacers along sidewalls of the gate feature and between the channel features;
- wherein a width of each of the gate regions between the channel features is substantially uniform and wherein a thickness of the gate regions varies by layers.
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A method for fabricating a semiconductor device, the method comprising:
- depositing alternating layers of a first semiconductor material and a second semiconductor material on a substrate, the first semiconductor material being a sacrificial material and the second semiconductor material comprising a channel material, wherein each layer of the first semiconductor material varies in characteristics;
- performing a patterning process to form a fin stack;
- partially laterally etching the first semiconductor material from the fin stack such that a width of remaining portions of the first semiconductor material is substantially uniform;
- and
- forming inner spacers on each of the remaining portions of the first semiconductor material such that a width of sidewall spacers increases towards the substrate;
- and
- forming a gate structure around each second semiconductor material such that a thickness of the gate structure between each second semiconductor material increases closer to the substrate.
4 more elements
Dependencies are inferred from the claim text.