# US 11,310,911 B2 · Three-dimensional (3D) integrated circuit (IC) integration of an embedded chip and a preformed metal routing structure

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- Number: US 11,310,911 B2
- Document ID: US11310911B2
- Status: Granted
- Kind: B2
- Application number: 16/929,004
- Filed: 2020-07-14
- Published: 2022-01-20
- Granted: 2022-04-19
- Earliest claimed: 2020-07-14
- Assignees: QUALCOMM Incorporated
- Applicants: QUALCOMM Incorporated
- Inventors: Stanley Seungchul Song; Jonghae Kim; Periannan Chidambaram
- Web page: https://patentgrep.com/patent/US11310911B2

## CPC

- H05K 1/111: {Pads for surface mounting, e.g. lay-out}
- H10W 70/614: {the multiple chips being integrally enclosed}
- G06F 1/189: {Power distribution}
- H05K 1/0284: {Details of three-dimensional rigid printed circuit boards (H05K1/119 takes precedence; shaping of the substrate H05K3/0014)}
- H05K 1/115: {Via connections; Lands around holes or via connections (H05K1/112 takes precedence)}
- H05K 3/101: {by casting or moulding of conductive material}
- H05K 3/4007: {Surface contacts, e.g. bumps (H05K3/4092 takes precedence; deposition of finish layers on pads H05K3/24; forming solder bumps H05K3/3465)}
- H05K 3/4038: {Through-connections; Vertical interconnect access [VIA] connections (H05K3/403, H05K3/42 take precedence)}
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/635: {Through-vias}
- H10W 90/00: Package configurations
- H05K 2203/1327: Moulding over PCB locally or completely
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

An integrated circuit (IC) package is described. The IC package includes a metallization structure. The IC package also includes a first die in a package substrate layer. The package substrate includes a first surface and a second surface, opposite the first surface. The second surface of the package substrate layer is on the metallization structure. The IC package further includes a second die on the first surface of the package substrate layer and on the first die. The IC package also includes through vias in the package substrate layer to couple pads of the second die to metal routing layers at a first surface of the metallization structure. The IC package further includes package bumps on a second surface of the metallization structure, opposite the first surface, and coupled to the pads of the second die through the metal routing layers.

## Claims

### Claim 1

An integrated circuit (IC) package, comprising:
a metallization structure;
a first die in a package substrate layer having a first surface and a second surface, opposite the first surface, the second surface of the package substrate layer on the metallization structure;
a second die on the first surface of the package substrate layer and on the first die, in which a performance level of the second die is greater than a performance level of the first die;
through vias in the package substrate layer to couple pads of the second die to metal routing layers at a first surface of the metallization structure; and
package bumps on a second surface of the metallization structure, opposite the first surface, and coupled to the pads of the second die through the metal routing layers.

### Claim 2 (depends on 1)

The IC package of claim 1, in which a first surface of the first die is coplanar with the first surface of the package substrate layer.

### Claim 3 (depends on 1)

The IC package of claim 1, in which a surface of the first die is directly bonded to a surface of the second die.

### Claim 4 (depends on 1)

The IC package of claim 1, in which the second die comprises a logic die and the first die comprises a memory die.

### Claim 5 (depends on 1)

The IC package of claim 1, in which a length of the second die is greater than a length of the first die.

### Claim 6 (depends on 1)

The IC package of claim 1, in which the package substrate layer comprises a mold layer and the through vias comprise through mold vias (TMVs).

### Claim 7 (depends on 6)

The IC package of claim 6, in which the mold layer comprises a spin-on oxide.

### Claim 8 (depends on 1)

The IC package of claim 1, in which the metallization structure is comprised of a plurality of the metal routing layers within dielectric layers including an organic layer.

### Claim 9 (depends on 1)

The IC package of claim 1, in which the package bumps comprise package solder balls.

### Claim 10

A method for fabricating stacked dies within an integrated circuit (IC) package, comprising:
encapsulating a first die in a package substrate layer having a first surface and a second surface, opposite the first surface;
forming through vias in the package substrate layer;
forming a metallization structure on the second surface of the package substrate layer;
bonding a second die to the first surface of the package substrate layer;
directly bonding a surface of the second die to a surface of the first die; and
forming package bumps on a surface of the metallization structure, opposite the package substrate layer, to contact pads of the second die through metal routing layers of the metallization structure.

### Claim 11 (depends on 10)

The method of claim 10, in which encapsulating comprises depositing a spin-on oxide layer to embed the first die in a mold layer.

### Claim 12 (depends on 11)

The method of claim 11, in which forming the through vias comprises forming through mold vias (TMVs) through the mold layer.

### Claim 13 (depends on 10)

The method of claim 10, in which forming the metallization structure comprises forming a plurality of the metal routing layers within dielectric layers including an organic layer on the second surface of the package substrate layer.

### Claim 14 (depends on 10)

The method of claim 10, further comprising depositing a mold layer on the second die and exposed portions of the first surface of the package substrate layer.

### Claim 15

An integrated circuit (IC) package, comprising:
a metallization structure;
means for storing data in a package substrate layer, having a first surface and a second surface, opposite the first surface, the second surface of the package substrate layer on the metallization structure, in which the package substrate layer comprises a mold layer, comprising a spin-on oxide;
an active die on the first surface of the package substrate layer and on the data storing means;
through vias in the package substrate layer to couple pads of the active die to metal routing layers at a first surface of the metallization structure; and
package bumps on a second surface of the metallization structure, opposite the first surface, and coupled to the pads of the active die through the metal routing layers.

### Claim 16 (depends on 15)

The IC package of claim 15, in which the metallization structure is comprised of a plurality of the metal routing layers within dielectric layers including an organic layer.

### Claim 17 (depends on 15)

The IC package of claim 15, in which the package bumps comprise package solder balls.