# US 11,310,904 B2 · Chip package and power module

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- Number: US 11,310,904 B2
- Document ID: US11310904B2
- Status: Granted
- Kind: B2
- Application number: 16/663,366
- Filed: 2019-10-25
- Published: 2020-04-30
- Granted: 2022-04-19
- Earliest claimed: 2018-10-30
- Assignees: Xintec Inc.
- Applicants: Xintec Inc.
- Inventors: Tsang-Yu Liu; Po-Han Lee; Wei-Ming Chien
- Web page: https://patentgrep.com/patent/US11310904B2

## CPC

- H05K 1/0215: {Grounding of printed circuits by connection to external grounding means}
- H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
- H05K 1/0346: {containing N}
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 70/635: {Through-vias}
- H10W 70/662: {Semiconductor materials}
- H05K 1/0254: {High voltage adaptations; Electrical insulation details; Overvoltage or electrostatic discharge protection (electrostatic discharge protection for electric apparatus in general H05K9/0067, H05K9/0079); Arrangements for regulating voltages or for using plural voltages}
- H05K 1/181: associated with surface mounted components
- H05K 2203/049: Wire bonding
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/874: {On different surfaces}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/794: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A chip package includes a high voltage withstanding substrate and a device chip. The high voltage withstanding substrate has a main body, a functional layer, and a grounding layer. The main body has a top surface, a bottom surface opposite the top surface, a through hole through the top surface and the bottom surface, and a sidewall surrounding the through hole. The functional layer is located on the top surface. The grounding layer covers the bottom surface and the sidewall. The device chip is located on the functional layer, and has a grounding pad that faces the main body. The grounding pad is electrically connected to the grounding layer in the through hole.

## Claims

### Claim 1

A chip package, comprising:
a high voltage withstanding substrate having a main body, a functional layer and a grounding layer, the main body having a top surface and a bottom surface opposite the top surface, a through hole through the top surface and the bottom surface, and a sidewall surrounding the through hole, wherein the functional layer is made of a material comprising gallium nitride (GaN) and is located on the top surface, and the grounding layer covers the bottom surface and the sidewall; and
a device chip located on the functional layer, and having a grounding pad that faces the main body, wherein the grounding pad is in contact with the functional layer and is electrically connected to the grounding layer in the through hole, and the grounding pad is further located in the functional layer.

### Claim 2 (depends on 1)

The chip package of claim 1, wherein a thickness of the functional layer is in a range from 3 μm to 4 μm.

### Claim 3 (depends on 1)

The chip package of claim 1, wherein the grounding layer substantially covers the entire bottom surface of the main body.

### Claim 4 (depends on 1)

The chip package of claim 1, wherein a region of the grounding layer is greater than an area of the grounding pad.

### Claim 5 (depends on 1)

The chip package of claim 1, wherein the grounding layer is made of a material comprising copper.

### Claim 6 (depends on 1)

The chip package of claim 1, wherein the device chip has a bottom surface that faces the functional layer, and the grounding pad is located on the bottom surface of the device chip.

### Claim 7 (depends on 1)

The chip package of claim 1, wherein the device chip has a bottom surface that faces the functional layer, and the grounding pad is located in the bottom surface of the device chip.

### Claim 8 (depends on 7)

The chip package of claim 7, wherein the through hole and the grounding layer further extend into the functional layer.

### Claim 9 (depends on 8)

The chip package of claim 8, wherein the through hole and the grounding layer further extend into the device chip.

### Claim 10 (depends on 1)

The chip package of claim 1, wherein the device chip has a top surface facing away from the functional layer, and the top surface of the device chip has a conductive pad.

### Claim 11

A power module, comprising:
a printed circuit board having a grounding region; and
a chip package located on the grounding region of the printed circuit board, comprising:
a high voltage withstanding substrate having a main body, a functional layer, and a grounding layer, the main body having a top surface and a bottom surface opposite the top surface, a through hole through the top surface and the bottom surface, and a sidewall surrounding the through hole, wherein the functional layer is made of a material comprising gallium nitride (GaN) and is located on the top surface, the grounding layer covers the bottom surface and the sidewall, and the grounding layer is located on the grounding region of the printed circuit board and is electrically connected to the grounding region; and
a device chip located on the functional layer, and having a grounding pad facing the main body, wherein the grounding pad is in contact with the functional layer and is electrically connected to the grounding layer in the through hole, and the grounding pad is further located in the functional layer.

### Claim 12 (depends on 11)

The power module of claim 11, wherein the printed circuit board has a wire bonding region, the device chip has a top surface facing away from the functional layer, the top surface of the device chip has a conductive pad, and the power module further comprises:
a conductive wire, wherein two ends of the conductive wire are respectively located on the wire bonding region and the conductive pad.

### Claim 13 (depends on 11)

The power module of claim 11, further comprising:
a bonding conductive layer located between the grounding layer of the high voltage withstanding substrate and the grounding region of the printed circuit board.

### Claim 14 (depends on 13)

The power module of claim 13, wherein the bonding conductive layer is silver paste or solder.