# US 11,310,450 B2 · Solid-state imaging element, imaging device, and method for controlling solid-state imaging element

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 11,310,450 B2
- Document ID: US11310450B2
- Status: Granted
- Kind: B2
- Application number: 17/250,337
- Filed: 2019-04-15
- Published: 2021-09-09
- Granted: 2022-04-19
- Earliest claimed: 2018-07-18
- Assignees: Sony Semiconductor Solutions Corporation
- Applicants: Sony Semiconductor Solutions Corporation
- Inventors: Chihiro Okada; Kouji Matsuura
- Web page: https://patentgrep.com/patent/US11310450B2

## CPC

- H03M 1/1245: {Details of sampling arrangements or methods}
- H03M 1/56: Input signal compared with linear ramp
- H04N 25/616: involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
- H04N 25/63: applied to dark current
- H04N 25/78: Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
- H04N 25/79: Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors
- H03M 1/123: {Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION

## Abstract

In a solid-state imaging element in which an ADC is disposed, deterioration of conversion accuracy of the ADC caused by a dark current is inhibited. A signal voltage sample-and-hold circuit samples and holds, as a sample signal voltage, a voltage obtained by dividing a difference between a voltage of a vertical signal line corresponding to a light reception amount in a pixel and a predetermined variable reference voltage. An analog-to-digital converter converts an analog signal corresponding to the sample signal voltage to a digital signal. A reference voltage control section performs control to modulate a value of the variable reference voltage according to a dark current amount in the pixel.

## Claims

### Claim 1

A solid-state imaging element, comprising:
a signal voltage sample-and-hold circuit configured to sample and hold, as a sample signal voltage, a voltage obtained by division of a difference between a first voltage of a vertical signal line corresponding to a light reception amount in a pixel and a determined variable reference voltage;
a reference voltage control section configured to perform control to modulate a value of the determined variable reference voltage according to a dark current amount in the pixel;
a reset voltage sample-and-hold circuit configured to sample and hold, as a sample reset voltage, a voltage obtained by division of a difference between a second voltage of the vertical signal line when the pixel is initialized and a determined fixed reference voltage;
a differential conversion circuit configured to:
convert a difference between the sample signal voltage and the sample reset voltage to a current signal; and
supply the current signal as an analog signal; and
an analog-to-digital converter configured to convert the analog signal to a digital signal.

### Claim 2 (depends on 1)

The solid-state imaging element according to claim 1, wherein
the pixel includes one of an effective pixel which is not shielded from light or a light shielded pixel which is shielded from the light, and
the reference voltage control section is further configured to measure the dark current amount from the digital signal corresponding to the light shielded pixel.

### Claim 3 (depends on 1)

The solid-state imaging element according to claim 1, further comprising:
a pixel array section including a plurality of pixels, wherein the plurality of pixels includes the pixel and is in a two-dimensional lattice-like shape; and
a pair of signal voltage sample-and-hold circuits and a pair of reset voltage sample-and-hold circuits that are disposed for each of columns that include the plurality of pixels and that are arranged in a determined direction in the pixel array section, wherein
during a sample period in a first signal voltage sample-and-hold circuit of the pair of signal voltage sample-and-hold circuits, a second signal voltage sample-and-hold circuit of the pair of signal voltage sample-and-hold circuits holds the sample signal voltage, and
during a sample period in a first reset voltage sample-and-hold circuit of the pair of reset voltage sample-and-hold circuits, a second reset voltage sample-and-hold circuit of the pair of reset voltage sample-and-hold circuits holds the sample reset voltage.

### Claim 4 (depends on 1)

The solid-state imaging element according to claim 1, wherein
the pixel is on a light receiving board, and
the signal voltage sample-and-hold circuit, the analog-to-digital converter, and the reference voltage control section are on a circuit board that is layered on the light receiving board.

### Claim 5 (depends on 4)

The solid-state imaging element according to claim 4, further comprising a memory configured to hold the digital signal, wherein the memory is on a memory board.

### Claim 6 (depends on 1)

The solid-state imaging element according to claim 1, further comprising a reference voltage generating section configured to:
generate the determined variable reference voltage under control of the reference voltage control section; and
supply the determined variable reference voltage to the signal voltage sample-and-hold circuit.

### Claim 7

An imaging device, comprising:
a signal voltage sample-and-hold circuit configured to sample and hold, as a sample signal voltage, a voltage obtained by division of a difference between a first voltage of a vertical signal line corresponding to a light reception amount in a pixel and a determined variable reference voltage;
a reference voltage control section configured to perform control to modulate a value of the determined variable reference voltage according to a dark current amount in the pixel;
a reset voltage sample-and-hold circuit configured to sample and hold, as a sample reset voltage, a voltage obtained by division of a difference between a second voltage of the vertical signal line when the pixel is initialized and a determined fixed reference voltage;
a differential conversion circuit configured to:
convert a difference between the sample signal voltage and the sample reset voltage to a current signal; and
supply the current signal as an analog signal;
an analog-to-digital converter configured to convert the analog signal to a digital signal; and
a digital signal processing circuit configured to process the digital signal.

### Claim 8

A method for controlling a solid-state imaging element, the method comprising:
sampling and holding, as a sample signal voltage, a voltage obtained by dividing a difference between a first voltage of a vertical signal line corresponding to a light reception amount in a pixel and a determined variable reference voltage;
performing control to modulate a value of the determined variable reference voltage according to a dark current amount in the pixel;
sampling and holding, as a sample reset voltage, a voltage obtained by dividing a difference between a second voltage of the vertical signal line when the pixel is initialized and a determined fixed reference voltage;
converting a difference between the sample signal voltage and the sample reset voltage to a current signal;
supplying the current signal as an analog signal; and
converting the analog signal to a digital signal.