# US 11,310,072 B2 · Bus transceiver with ring suppression > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,310,072 B2 - Document ID: US11310072B2 - Status: Granted - Kind: B2 - Application number: 17/063,450 - Filed: 2020-10-05 - Published: 2021-06-03 - Granted: 2022-04-19 - Earliest claimed: 2019-12-03 - Assignees: Texas Instruments Incorporated - Applicants: Texas Instruments Incorporated - Inventors: Richard Sterling Broughton; Vijayalakshmi Devarajan; Wesley Ryan Ray; Dushmantha Bandara Rajapaksha - Web page: https://patentgrep.com/patent/US11310072B2 ## CPC - H04L 12/40013: {Details regarding a bus controller} - H04L 25/0272: {Arrangements for coupling to multiple lines, e.g. for differential transmission} - H04M 3/02: Calling substations, e.g. by ringing (selective calling H04Q) - H04L 2012/40215: {Controller Area Network CAN} - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - H04M: TELEPHONIC COMMUNICATION (circuits for controlling other apparatus via a telephone cable and not involving telephone switching apparatus G08) ## Abstract A transceiver includes a driver stage and a transient-triggered ring suppression circuit. The driver stage has a first transistor coupled between a supply voltage terminal and a first bus terminal and a second transistor coupled between a ground and a second bus terminal. The transient-triggered ring suppression circuit is coupled to the first and second transistors. The transient-triggered ring suppression circuit is configured to be enabled upon transition of the transceiver from a dominant state to a recessive state. Further, while the transceiver is in the recessive state, the transient-triggered ring suppression circuit is configured to attenuate ringing on at least one of the first or second bus terminals. ## Claims ### Claim 1 A transceiver, comprising: a driver stage having a first transistor coupled between a supply voltage terminal and a first bus terminal and a second transistor coupled between a ground and a second bus terminal; a third transistor coupled between a common voltage terminal and a terminal of the first transistor, the first transistor having a control input and first and second current terminals; a first capacitor coupled between the first current terminal and a control input of the third transistor; a first resistor coupled between the supply voltage terminal and the control input of the third transistor; and a first switch coupled between the supply voltage terminal and the control input of the third transistor. ### Claim 2 (depends on 1) The transceiver of claim 1, wherein a second switch is configured to be on during a first state of the transceiver, and off during a second state of the transceiver. ### Claim 3 (depends on 2) The transceiver of claim 2, wherein the transceiver is a controller area network (CAN) bus transceiver, and the first state is a dominant state and the second state is a recessive state. ### Claim 4 (depends on 1) The transceiver of claim 1, further including a voltage buffer having an output coupled to the common voltage terminal. ### Claim 5 (depends on 1) The transceiver of claim 1, further including: a fourth transistor coupled between a terminal of the second transistor and the common voltage terminal, the fourth transistor having a control input and first and second current terminals; a second capacitor coupled between the first current terminal of the fourth transistor and the control input of the fourth transistor; a second resistor coupled between the ground and the control input of the fourth transistor; and a second switch coupled between the ground and the control input of the fourth transistor. ### Claim 6 (depends on 5) The transceiver of claim 5, wherein the first transistor has a control input and the second transistor includes a control input, and the transceiver further includes a transmitter driver having a driver input, a first output, and a second output, the driver input configured to receive a transmit signal, the first output is coupled to the control input of the first transistor, and the second output is coupled to the control input of the second transistor. ### Claim 7 (depends on 5) The transceiver of claim 5, wherein: the first switch is configured to be on during a first state of the transceiver, and off during a second state of the transceiver; and the second switch is configured to be on during the first state of the transceiver, and off during the second state of the transceiver. ### Claim 8 (depends on 7) The transceiver of claim 7, wherein: the transceiver is a controller area network (CAN) bus transceiver, and the first state is a dominant state and the second state is a recessive state; and the transceiver includes a voltage buffer having an output providing the common voltage terminal. ### Claim 9 (depends on 1) The transceiver of claim 1, wherein the first transistor has a current terminal and the second transistor has a current terminal, and the transceiver further includes a recessive nulling circuit coupled to the common voltage terminal, the current terminal of the first transistor, and the current terminal of the second transistor, and the recessive nulling circuit is configured to force the current terminals of the first and second transistors to a voltage on the common voltage terminal for a period of time upon transition of the transceiver from a dominant state to a recessive state. ### Claim 10 A transceiver, comprising: a driver stage having a first transistor coupled between a supply voltage terminal and a first bus terminal and a second transistor coupled between a ground and a second bus terminal; and a transient-triggered ring suppression circuit coupled to the first and second transistors, the transient-triggered ring suppression circuit is configured to be enabled upon transition of the transceiver from a dominant state to a recessive state and, while the transceiver is in the recessive state, to attenuate ringing on at least one of the first or second bus terminals; wherein the transient-triggered ring suppression circuit includes: a third transistor coupled between a terminal of the second transistor and a common voltage terminal, the third transistor having a control input and first and second current terminals; a first capacitor coupled between the second current terminal of the third transistor and the control input of the third transistor; a first resistor coupled between the ground and the control input of the third transistor; and a first switch coupled between the ground and the control input of the third transistor. ### Claim 11 (depends on 10) The transceiver of claim 10, wherein the transient-triggered ring suppression circuit includes: a fourth transistor coupled between a common voltage terminal and a terminal of the first transistor, the fourth transistor having a control input and first and second current terminals; a second capacitor coupled between the first current terminal and the control input of the fourth transistor; a second resistor coupled between the supply voltage terminal and the control input of the fourth transistor; and a second switch coupled between the supply voltage terminal and the control input of the fourth transistor. ### Claim 12 (depends on 10) The transceiver of claim 10, wherein the first switch is configured to be on during the dominant state, and off the recessive state. ### Claim 13 (depends on 10) The transceiver of claim 10, further including a voltage buffer having an output coupled to the common voltage terminal. ### Claim 14 A transceiver, comprising: a driver stage having a first transistor coupled between a supply voltage terminal and a first bus terminal and a second transistor coupled between a ground and a second bus terminal; and a transient-triggered ring suppression circuit coupled to the first and second transistors, the transient-triggered ring suppression circuit is configured to be enabled upon transition of the transceiver from a dominant state to a recessive state and, while the transceiver is in the recessive state, to attenuate ringing on at least one of the first or second bus terminals; wherein the transient-triggered ring suppression circuit includes: a third transistor coupled between a common voltage terminal and a terminal of the first transistor, the first transistor having a control input and first and second current terminals; a first capacitor coupled between the first current terminal and the control input of the third transistor; a first resistor coupled between the supply voltage terminal and the control input of the third transistor; and a first switch coupled between the supply voltage terminal and the control input of the third transistor. ### Claim 15 A transceiver, comprising: a driver stage having a first transistor coupled between a supply voltage terminal and a first bus terminal and a second transistor coupled between a ground and a second bus terminal; a third transistor coupled between a common voltage terminal and a terminal of the first transistor, the first transistor having a control input and first and second current terminals; a first capacitor coupled between the first current terminal and the control input of the third transistor; a first resistor coupled between the supply voltage terminal and the control input of the third transistor; a first switch coupled between the supply voltage terminal and the control input of the third transistor; a fourth transistor coupled between a terminal of the second transistor and the common voltage terminal, the fourth transistor having a control input and first and second current terminals; a second capacitor coupled between the first current terminal of the fourth transistor and the control input of the fourth transistor; a second resistor coupled between the ground and the control input of the fourth transistor; and a second switch coupled between the ground and the control input of the fourth transistor. ### Claim 16 (depends on 15) The transceiver of claim 15, further including a voltage buffer having an output coupled to the second current terminals of the third and fourth transistors, the voltage buffer configured to generate a common voltage on the common voltage terminal. ### Claim 17 (depends on 16) The transceiver of claim 16, wherein the first transistor has a current terminal and the second transistor has a current terminal, and the transceiver further includes a recessive nulling circuit coupled to the common voltage terminal, the current terminal of the first transistor, and the current terminal of the second transistor, and the recessive nulling circuit is configured to force the current terminals of the first and second transistors to the common voltage terminal for a period of time upon transition of the transceiver from a first state to a second state. ### Claim 18 (depends on 15) The transceiver of claim 15, wherein the transceiver is a controller area network (CAN) bus transceiver.