# US 11,309,995 B2 · Parallel channel skew for enhanced error correction > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,309,995 B2 - Document ID: US11309995B2 - Status: Granted - Kind: B2 - Application number: 16/793,746 - Filed: 2020-02-18 - Published: 2021-01-14 - Granted: 2022-04-19 - Earliest claimed: 2019-07-11 - Assignees: Credo Technology Group Limited - Applicants: Credo Technology Group Limited - Inventors: Junqing Sun; Haoli Qian - Web page: https://patentgrep.com/patent/US11309995B2 ## CPC - H04L 1/0061: {Error detection codes} - H04L 25/4917: {using multilevel codes} - H03M 9/00: Parallel/series conversion or vice versa (digital stores in which the information is moved stepwise per se G11C19/00) - H04L 1/0041: {Arrangements at the transmitter end} - H04L 1/0058: {Block-coded modulation} - H04L 25/026: {Arrangements for coupling transmitters, receivers or transceivers to transmission lines; Line drivers (duplexing arrangements H04L5/14)} - H04L 25/0272: {Arrangements for coupling to multiple lines, e.g. for differential transmission} - H04L 25/03872: {Parallel scrambling or descrambling} - H04L 25/03878: {Line equalisers; line build-out devices} - H04L 2001/0096: {Channel splitting in point-to-point links} - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract Digital communication transmitters, systems, and methods can introduce skew into parallel transmission channels to enhance the performance of forward error correction (FEC) decoders. One illustrative serializer-deserializer (SerDes) transmitter embodiment includes: a block code encoder configured to convert a sequence of input data blocks into a sequence of encoded data blocks; a demultiplexer configured to distribute code symbols from the sequence of encoded data blocks to multiple lanes in a cyclical fashion, the multiple lanes corresponding to parallel transmission channels; a skewer configured to buffer the multiple lanes to provide respective lane delays, the lane delays differing from each other by no less than half an encoded data block period; and multiple drivers, each driver configured to transmit code symbols from one of said multiple lanes on a respective one of said parallel transmission channels. ## Claims ### Claim 1 An active cable that comprises electrical conductors joining a first transceiver to a second transceiver to provide parallel transmission channels therebetween, each of the first and second transceivers including: a block code encoder configured to convert a sequence of input data blocks into a sequence of encoded data blocks; a demultiplexer configured to distribute code symbols from the sequence of encoded data blocks to multiple lanes in a cyclical fashion; a skewer configured to buffer the multiple lanes to provide respective lane delays, the lane delays differing from each other by no less than half an encoded data block period; and multiple drivers each configured to transmit code symbols from one of said multiple lanes on a respective one of said parallel transmission channels. ### Claim 2 (depends on 1) The active cable of claim 1, wherein each of the first and second transceivers further include: multiple receivers each configured to convert a receive signal from a respective one of said transmission channels into a sequence of channel symbols; an alignment module configured to align the multiple sequences of channel symbols using alignment markers to form a sequence of received data blocks; and a block code decoder configured to convert the received data blocks into a sequence of output data blocks. ### Claim 3 (depends on 2) The active cable of claim 2, wherein each of the first and second transceivers further includes a deskewer preceding the alignment module, the deskewer being configured to buffer the multiple sequences of channel symbols by predetermined amounts to compensate for the lane delays provided by the skewer. ### Claim 4 (depends on 1) The active cable of claim 1, wherein the lane delays correspond to integer multiples of an encoded data block period. ### Claim 5 (depends on 4) The active cable of claim 4, wherein the multiple lanes comprise four lanes. ### Claim 6 (depends on 1) The active cable of claim 1, wherein the block code encoder is a Reed-Solomon encoder, and the code symbols each comprise 10 bits. ### Claim 7 (depends on 6) The active cable of claim 6, wherein the multiple drivers each transmit the code symbols as a sequence of NRZ channel symbols. ### Claim 8 (depends on 6) The active cable of claim 6, wherein the multiple drivers each transmit the code symbols as a sequence of PAM4 channel symbols. ### Claim 9 A SerDes transmitter that comprises: a block code encoder configured to convert a sequence of input data blocks into a sequence of encoded data blocks; a demultiplexer configured to distribute code symbols from the sequence of encoded data blocks to multiple lanes in a cyclical fashion, the multiple lanes corresponding to parallel transmission channels; a skewer configured to buffer the multiple lanes to provide respective lane delays, the lane delays differing from each other by no less than half an encoded data block period; and multiple drivers, each driver configured to transmit code symbols from one of said multiple lanes on a respective one of said parallel transmission channels. ### Claim 10 (depends on 9) The transmitter of claim 9, wherein the block code encoder is a Reed-Solomon encoder, and the code symbols each comprise 10 bits. ### Claim 11 (depends on 10) The transmitter of claim 10, wherein the multiple drivers each transmit the code symbols as a sequence of NRZ channel symbols. ### Claim 12 (depends on 10) The transmitter of claim 10, wherein the multiple drivers each transmit the code symbols as a sequence of PAM4 channel symbols. ### Claim 13 (depends on 9) The transmitter of claim 9, wherein the lane delays correspond to integer multiples of a base delay amount. ### Claim 14 (depends on 13) The transmitter of claim 13, wherein the base delay amount is an encoded data block period. ### Claim 15 (depends on 13) The transmitter of claim 13, wherein the multiple lanes comprise four lanes. ### Claim 16 A digital communication method that comprises: encoding a sequence of input data blocks into a sequence of encoded data blocks; distributing the sequence of encoded data blocks in symbol-by-symbol fashion across multiple lanes corresponding to parallel transmission channels; buffering the multiple lanes to provide respective lane delays, the lane delays differing from each other by no less than half an encoded data block period; and driving the parallel transmission channels each with symbols from a respective one of the multiple lanes. ### Claim 17 (depends on 16) The method of claim 16, further comprising: converting receive signals from the multiple lanes into multiple sequences of channel symbols; buffering the multiple sequences by predetermined amounts to compensate for said respective lane delays; using alignment markers to align the multiple sequences to form a sequence of received data blocks; and decoding the sequence of received data blocks into a sequence of output data blocks. ### Claim 18 (depends on 16) The method of claim 16, wherein the lane delays correspond to integer multiples of a base delay amount. ### Claim 19 (depends on 18) The method of claim 18, wherein the base delay amount is an encoded data block period. ### Claim 20 (depends on 18) The method of claim 18, wherein the multiple lanes comprise four lanes.