# US 11,309,926 B2 · Multiple band multiple mode transceiver front end flip-chip architecture and circuitry with integrated power amplifiers > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,309,926 B2 - Document ID: US11309926B2 - Status: Granted - Kind: B2 - Application number: 16/683,662 - Filed: 2019-11-14 - Published: 2020-03-12 - Granted: 2022-04-19 - Earliest claimed: 2013-04-24 - Assignees: Skyworks Solutions, Inc. - Applicants: Skyworks Solutions, Inc. - Inventors: Lisette L. Zhang; Oleksandr Gorbachov - Web page: https://patentgrep.com/patent/US11309926B2 ## CPC - H04B 1/0475: {with means for limiting noise, interference or distortion (H04B1/0483 takes precedence)} - H03F 3/195: in integrated circuits - H03F 3/213: in integrated circuits - H03F 3/24: of transmitter output stages - H04B 1/16: Circuits - H04B 1/40: Circuits - H10W 20/497: {Inductive arrangements or effects of, or between, wiring layers} - H10W 44/20: at high-frequency [HF] or radio frequency [RF] - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H03F 2200/294: the amplifier being a low noise amplifier [LNA] - H03F 2200/451: the amplifier being a radio frequency amplifier - H03F 2200/465: Power sensing - H04B 1/0067: {with one or more circuit blocks in common for different bands} - H04B 2001/0408: {with power amplifiers} - H10W 44/226: {for HF amplifiers} - H10W 44/234: {Arrangements for impedance matching} - H10W 44/241: {for passive devices or passive elements} - H10W 44/248: {for antennas} - H10W 44/255: {for operation at multiple different frequencies} - H10W 70/65: Shapes or dispositions of interconnections - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/932: {Plan-view shape, i.e. in top view} - H10W 72/9445: {Top-view layouts, e.g. mirror arrays} - H04B: TRANSMISSION - H03F: AMPLIFIERS - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract An integrated circuit architecture and circuitry is defined by a die structure with a plurality of exposed conductive pads arranged in a grid of rows and columns. The die structure has a first operating frequency region with a first transmit and receive chain, and a second operating frequency region with a second transmit chain and a second receive chain. There is a shared region of the die structure defined by an overlapping segment of the first operating frequency region and the second operating frequency region with a shared power supply input conductive pad connected to the first transmit chain, the second transmit chain, the first receive chain, and the second receive chain, and a shared power detection output conductive pad connected to the first transmit chain and the second transmit chain. ## Claims ### Claim 1 An integrated circuit architecture comprising: a first operating frequency region corresponding to a first physical area on a die, the first operating frequency region including a first transmit chain and a first receive chain; a second operating frequency region corresponding to a second physical area on the die, the second operating frequency region including a second transmit chain and a second receive chain; a shared region of the die corresponding to a third physical area on the die disposed between the first physical area and the second physical area and including a control input conductive pad connected to both the first transmit chain and the second transmit chain; and a voltage regulator disposed in the shared region of the die and connected to the first transmit chain and the first receive chain and to the second transmit chain and the second receive chain. ### Claim 2 (depends on 1) The integrated circuit architecture of claim 1 wherein the first transmit chain includes at least one first operating frequency power amplifier. ### Claim 3 (depends on 2) The integrated circuit architecture of claim 2 wherein the second transmit chain includes at least one second operating frequency power amplifier. ### Claim 4 (depends on 1) The integrated circuit architecture of claim 1 wherein the first receive chain includes at least one first operating frequency low noise amplifier. ### Claim 5 (depends on 4) The integrated circuit architecture of claim 4 wherein the second receive chain includes at least one second operating frequency low noise amplifier. ### Claim 6 (depends on 1) The integrated circuit architecture of claim 1 further comprising a coplanar inductor defined by a terminal connected to the control input conductive pad, and a conductive trace wound around a periphery of the control input conductive pad in a spiral. ### Claim 7 An integrated circuit architecture comprising: a first operating frequency region corresponding to a first physical area on a die, the first operating frequency region including a first transmit chain and a first receive chain; a second operating frequency region corresponding to a second physical area on the die, the second operating frequency region including a second transmit chain and a second receive chain; a shared region of the die corresponding to a third physical area on the die disposed between the first physical area and the second physical area and including a control input conductive pad connected to both the first receive chain and the second receive chain; and a voltage regulator disposed in the shared region of the die and connected to the first transmit chain and the first receive chain and to the second transmit chain and the second receive chain. ### Claim 8 (depends on 7) The integrated circuit architecture of claim 7 wherein the first transmit chain includes at least one first operating frequency power amplifier. ### Claim 9 (depends on 8) The integrated circuit architecture of claim 8 wherein the second transmit chain includes at least one second operating frequency power amplifier. ### Claim 10 (depends on 7) The integrated circuit architecture of claim 7 wherein the first receive chain includes at least one first operating frequency low noise amplifier. ### Claim 11 (depends on 10) The integrated circuit architecture of claim 10 wherein the second receive chain includes at least one second operating frequency low noise amplifier. ### Claim 12 (depends on 7) The integrated circuit architecture of claim 7 further comprising a coplanar inductor defined by a terminal connected to the control input conductive pad, and a conductive trace wound around a periphery of the control input conductive pad in a spiral. ### Claim 13 An integrated circuit architecture comprising: a first operating frequency region corresponding to a first physical area on a die, the first operating frequency region including a first transmit chain and a first receive chain; a second operating frequency region corresponding to a second physical area on the die, the second operating frequency region including a second transmit chain and a second receive chain; a shared region of the die corresponding to a third physical area on the die disposed between the first physical area and the second physical area and including a shared power detection output conductive pad connected to the first transmit chain and the second transmit chain; a first power detector circuit disposed on the shared region of the die and connected to the shared power detection output conductive pad, an input of the first power detector circuit being connected to an output of the first transmit chain; a second power detector circuit disposed on the shared region of the die and connected to the shared power detection output conductive pad, an input of the second power detector circuit being connected to an output of the second transmit chain; and a voltage regulator disposed in the shared region of the die and connected to the first transmit chain and the first receive chain and to the second transmit chain and the second receive chain. ### Claim 14 (depends on 13) The integrated circuit architecture of claim 13 wherein the first transmit chain includes at least one first operating frequency power amplifier. ### Claim 15 (depends on 14) The integrated circuit architecture of claim 14 wherein the second transmit chain includes at least one second operating frequency power amplifier. ### Claim 16 (depends on 13) The integrated circuit architecture of claim 13 wherein the first receive chain includes at least one first operating frequency low noise amplifier. ### Claim 17 (depends on 16) The integrated circuit architecture of claim 16 wherein the second receive chain includes at least one second operating frequency low noise amplifier. ### Claim 18 (depends on 13) The integrated circuit architecture of claim 13 further comprising a coplanar inductor defined by a terminal connected to the shared power detection output conductive pad, and a conductive trace wound around a periphery of the shared power detection output conductive pad in a spiral. ### Claim 19 (depends on 13) The integrated circuit architecture of claim 13 wherein the first power detector circuit includes a first power detector amplifier circuit and the second power detector circuit includes a second power detector amplifier circuit. ### Claim 20 (depends on 13) The integrated circuit architecture of claim 13 wherein the first power detector circuit and the second power detector circuit include a common power detector amplifier circuit.