Efficient implementation of a threshold modified min-sum algorithm for low-density parity-check decoders
AssigneeArrowhead Center, Inc.
InventorsDavid G. Mitchell, Yanfang Liu
Life of this patent
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Abstract
A hardware efficient implementation of a threshold modified attenuated min-sum algorithm (TAMSA”) and a threshold modified offset min-sum algorithm (“TOMSA”) that improve the performance of a low density parity-check (“LDPC”) decoder by reducing the bit error rate (“BER”) compared to the conventional attenuated min-sum algorithm (“AMSA”), offset min-sum algorithm (“OMSA”), and the min-sum algorithm (“MSA”). Embodiments of the present invention preferably use circuit optimization techniques, including a parallel computing structure and lookup tables, and a field-programmable gate array (“FPGA”) or application specific integrated circuit (“ASIC”) implementation.
Claims26
A method for implementing a threshold modified min-sum algorithm for a low-density parity check (“LDPC”) decoder comprising:
- quantization of received channel values;
- obtaining parallel input data;
- storing the parallel input data;
- based on data contained in a parity check matrix, a decoding controller causing an address generator to generate addresses to access stored data;
- passing data to a check node unit (“CNU”);
- the CNU calculating a minimum value of the data passed to the CNU;
- applying an offset value and/or attenuation value to the calculated minimum value if a magnitude of the calculated minimum value comprises a magnitude less than a threshold value and not applying the offset value and/or attenuation value to the magnitude of the calculated minimum value if the magnitude of the calculated minimum value is greater than the threshold value;
- storing the calculated minimum value;
- calculating iterations of variable node log-likelihood ratios (“LLRs”) and storing the calculated iterations of LLRs;
- after each iteration, making a hard decision based on a sign of the calculated iteration of the variable node LLR to determine whether a codeword is valid;
- and
- when the hard decision determines that the codeword is valid, passing final data to an output.
A method for implementing a threshold modified min-sum algorithm for a low-density parity check (“LDPC”) decoder comprising:
- a check node unit calculating minimum and sub-minimum values of data, including converting log-likelihood ratios (“LLRs”) into serial data and converting minimum data into serial data;
- the check node unit subtracting the minimum data from the LLRs via a plurality of full subtractor modules;
- storing calculated minimum and sub-minimum values;
- applying an offset value and/or attenuation value to the calculated minimum value if a magnitude of the calculated minimum value comprises a magnitude less than a threshold value and not applying the offset value and/or attenuation value to the magnitude of the calculated minimum value if the magnitude of the calculated minimum value is greater than the threshold value and
- after at each iteration, making a hard decision based on a sign of the calculated iteration of the variable node log-likelihood ratio to determine whether a codeword is valid.
Dependencies are inferred from the claim text.