# US 11,309,900 B2 · Monitor circuitry for power management and transistor aging tracking > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,309,900 B2 - Document ID: US11309900B2 - Status: Granted - Kind: B2 - Application number: 16/913,933 - Filed: 2020-06-26 - Published: 2021-12-30 - Granted: 2022-04-19 - Earliest claimed: 2020-06-26 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Kuan-Yueh Shen; Nasser A. Kurd; John Fallin - Web page: https://patentgrep.com/patent/US11309900B2 ## CPC - H03L 7/087: using at least two phase detectors or a frequency and phase detector in the loop - H03L 7/0992: {comprising a counter or a frequency divider} - H01R 13/665: {with built-in electronic circuit (H01R13/70, H01R13/719 take precedence)} - H03L 7/0816: {the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input} - H03L 7/0893: {the up-down pulses controlling at least two source current generators or at least two sink current generators connected to different points in the loop} - H03L 7/095: using a lock detector (H03L7/087 takes precedence) - H03L 7/101: {using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop (H03L7/113, H03L7/187 take precedence)} - H03L 7/1072: {by changing characteristics of the charge pump, e.g. changing the gain} - H03L 7/1075: {by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth (H03L7/1072 takes precedence)} - H03L 7/189: comprising a D/A converter for generating a coarse tuning voltage - H01R 2201/06: for computer periphery - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) - H01R: ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS ## Abstract Some embodiments include apparatuses having a first path in a phase locked loop, the first path including a phase frequency detector to receive a first signal having a first frequency and a first node to provide a voltage; an oscillator coupled to a second node and the first node to provide a second signal having a second frequency at the second node; a second path including a frequency divider coupled to the second node and the phase frequency detector; and a circuit to generate digital information having a value based on a value of the voltage at the second node. ## Claims ### Claim 1 An apparatus comprising: a first path in a phase locked loop, the first path including a phase frequency detector to receive a first signal having a first frequency and a first node to provide a voltage; an oscillator coupled to a second node and the first node to provide a second signal having a second frequency at the second node; a second path including a frequency divider coupled to the second node and the phase frequency detector; and a circuit to generate digital information having a value based on a value of the voltage at the second node. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the digital information has a first value corresponding to a first value of the voltage at the second node, and a second value corresponding to a second value of the voltage at the second node. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the oscillator is configured to provide a third signal having a third frequency. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the first path includes a charge pump coupled to the phase frequency detector, and a filter coupled to the charge pump. ### Claim 5 (depends on 4) The apparatus of claim 4, wherein the charge pump includes a nod to receive a current, the current having a value based on a value of the voltage at the first node. ### Claim 6 (depends on 1) The apparatus of claim 1, further comprising a die and an additional circuit on the die, wherein the phase locked loop is located on the die, and wherein: the additional circuit includes a logic gate coupled to a supply node of the additional circuit; and the oscillator includes a replica of the additional circuit, the replica of the additional circuit including a replica of the logic gate, the replica of the logic gate coupled to the second node. ### Claim 7 An apparatus comprising: a phase frequency detector to receive a first signal having a first frequency, a charge pump coupled to the phase frequency detector, a filter coupled to the charge pump, and a circuit coupled to the filter, the circuit including a circuit node to provide a voltage; a first circuit to generate a first oscillating signal, the first circuit including a first node, and a first additional node to provide the first oscillating signal; a second circuit to generate a second oscillating signal, the second circuit including a second node, and a second additional node to provide the second oscillating signal; a first switch coupled between the circuit node and the first node of the first circuit; a second switch coupled between the circuit node and the second node of the second circuit; a frequency divider coupled between the phase frequency detector and each of the first additional node and the second additional node; and an analog-to-digital converter coupled to circuit node. ### Claim 8 (depends on 7) The apparatus of claim 7, wherein each of the first and second switches includes a first terminal coupled to the circuit node, and wherein: the first circuit includes a first transistor having a non-gate terminal coupled to a second terminal of the first switch; and the second circuit includes a second transistor having a non-gate terminal coupled to a second terminal of the second switch. ### Claim 9 (depends on 7) The apparatus of claim 7, further comprising: a third circuit to generate a third oscillating signal, the third circuit including a third node, and a third additional node to provide the third oscillating signal; and a third switch coupled between the circuit node and the third node. ### Claim 10 (depends on 7) The apparatus of claim 7, further comprising a transistor having a gate coupled to the circuit node, and source and drain terminals coupled between a supply node and ground. ### Claim 11 (depends on 10) The apparatus of claim 10, further comprising a first additional transistor and a second additional transistor coupled in series with the first additional transistor between the charge pump and the supply node. ### Claim 12 An apparatus comprising: a first circuit on a die and a second circuit on the die; a phase frequency detector on a circuit path on the die to receive a first signal having a first frequency, the circuit path including a circuit node to provide a voltage; a first additional circuit on the die and coupled to the circuit node, the first additional circuit including replica of the first circuit, and a first output node to provide a first oscillating signal; a second additional circuit on the die and coupled to the circuit node, the second additional circuit including a replica of the second circuit, and a second output node to provide a second oscillating signal; a frequency divider coupled to the phase frequency detector and to each of the first and second output nodes; and an analog-to-digital converter coupled to circuit node. ### Claim 13 (depends on 12) The apparatus of claim 12, wherein each of the first and second additional circuits includes at least one logic gates. ### Claim 14 (depends on 12) The apparatus of claim 12, wherein: the first circuit includes a first logic gate and a second logic gate coupled between a first node and a second node of the first circuit; and the first additional circuit includes a replica of the first logic gate and a replica of the second logic gate coupled between a first node and a second node of the first additional circuit. ### Claim 15 (depends on 14) The apparatus of claim 14, wherein the first additional circuit includes an inverter coupled between the second node of the first additional circuit and the first output node. ### Claim 16 An apparatus comprising: a processor including a processing circuitry and a phase locked loop coupled to the processing circuitry, the processing circuitry including a logic circuit path, the phase locked loop including: a first path including a phase frequency detector to receive a first signal having a first frequency and a first node to provide a voltage; an oscillator coupled to a second node and the first node to provide a second signal having a second frequency at the second node; a second path including a frequency divider coupled to the second node and the phase frequency detector; and a circuit to generate digital information having a value based on a value of a voltage at the second node. ### Claim 17 (depends on 16) The apparatus of claim 16, further comprising a connector coupled to the processor, the connector conforming with one of Universal Serial Bus (USB), High-Definition Multimedia interface (HDMI), Thunderbolt, Peripheral Component Interconnect Express (PCIe), and Ethernet specifications.