# US 11,309,898 B2 · Semiconductor integrated circuit

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 11,309,898 B2
- Document ID: US11309898B2
- Status: Granted
- Kind: B2
- Application number: 17/167,374
- Filed: 2021-02-04
- Published: 2021-05-27
- Granted: 2022-04-19
- Earliest claimed: 2018-08-09
- Assignees: Olympus Corporation
- Applicants: Olympus Corporation
- Inventors: Yutaka Murata; Akira Ueno
- Web page: https://patentgrep.com/patent/US11309898B2

## CPC

- H03L 7/0812: {and where no voltage or current controlled oscillator is used}
- H03L 7/099: concerning mainly the controlled oscillator of the loop
- G06F 1/10: Distribution of clock signals {, e.g. skew}
- H03K 5/00: Manipulating of pulses not covered by one of the other main groups of this subclass (circuits with regenerative action H03K3/00, H03K4/00; by the use of non-linear magnetic or dielectric devices H03K3/45)
- H03L 7/22: using more than one loop
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A semiconductor integrated circuit includes: a phase synchronization circuit configured to be synchronized with a reference clock signal and to generate a synchronization clock signal by multiplying the reference clock signal; an edge detection circuit configured to detect an edge at which a signal waveform of the reference clock signal changes at a timing of the synchronization clock signal and to output an edge detection signal indicating the timing at which the edge has been detected; and a clock division circuit configured to be reset at a timing based on the edge detection signal and to generate a divided clock signal by dividing the synchronization clock signal.

## Claims

### Claim 1

A semiconductor integrated circuit, comprising:
a phase synchronization circuit configured to be synchronized with a reference clock signal and to generate a synchronization clock signal by multiplying the reference clock signal;
an edge detection circuit configured to detect an edge at which a signal waveform of the reference clock signal changes at a timing based on the synchronization clock signal and to output an edge detection signal indicating the timing at which the edge has been detected; and
a clock division circuit configured to be reset at a timing based on the edge detection signal and to generate a divided clock signal by dividing the synchronization clock signal.

### Claim 2 (depends on 1)

The semiconductor integrated circuit according to claim 1, wherein the edge detection circuit outputs the edge detection signal corresponding to one period of the synchronization clock signal.

### Claim 3 (depends on 2)

The semiconductor integrated circuit according to claim 2, further comprising:
a delay adjuster configured to delay the edge detection signal in the units of periods of the synchronization clock signal.

### Claim 4 (depends on 3)

The semiconductor integrated circuit according to claim 3, further comprising:
a delayer configured to simulate a propagation delay in a path of the divided clock signal and to delay the divided clock signal by a time corresponding to the propagation delay; and
a phase comparator configured to compare a phase of the divided clock signal delayed by the delayer with a phase of the reference clock signal.

### Claim 5 (depends on 4)

The semiconductor integrated circuit according to claim 4, wherein the delay adjuster delays the edge detection signal by a time corresponding to a period of the synchronization clock signal which is set based on a phase comparison result from the phase comparator.

### Claim 6 (depends on 5)

The semiconductor integrated circuit according to claim 5, further comprising:
a fine delay adjuster configured to delay the divided clock signal by a time in one period of the synchronization clock signal,
wherein the delayer further delays the divided clock signal delayed by the fine delay adjuster by the time corresponding to the propagation delay.

### Claim 7 (depends on 6)

The semiconductor integrated circuit according to claim 6, wherein the fine delay adjuster delays the divided clock signal by a time which is set based on the phase comparison result from the phase comparator.

### Claim 8 (depends on 1)

The semiconductor integrated circuit according to claim 1, further comprising:
a controller configured to cause the edge detection circuit to start detection of the edge.

### Claim 9 (depends on 3)

The semiconductor integrated circuit according to claim 3, further comprising:
a controller configured to cause the edge detection circuit to start detection of the edge and to set a time by which the edge detection signal is delayed in the delay adjuster.

### Claim 10 (depends on 4)

The semiconductor integrated circuit according to claim 4, further comprising:
a controller configured to cause the edge detection circuit to start detection of the edge and to set a time by which the edge detection signal is delayed in the delay adjuster based on the phase comparison result from the phase comparator.

### Claim 11 (depends on 6)

The semiconductor integrated circuit according to claim 6, further comprising:
a controller configured to cause the edge detection circuit to start detection of the edge, to set a time by which the edge detection signal is delayed in the delay adjuster based on the phase comparison result from the phase comparator, and to set a time by which the divided clock signal is delayed in the fine delay adjuster.