# US 11,309,896 B2 · Reconfigurable logic circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,309,896 B2 - Document ID: US11309896B2 - Status: Granted - Kind: B2 - Application number: 16/766,170 - Filed: 2018-11-19 - Published: 2020-11-19 - Granted: 2022-04-19 - Earliest claimed: 2017-11-22 - Assignees: Katholieke Universiteit Leuven; Università Della Svizzera Italiana; Ecole Polytechnique Federale De Lausanne (Epfl) - Applicants: Katholieke Universiteit Leuven; Ecole Polytechnique FéDéRale De Lausanne (Epfl); Università Della Svizzera Italiana - Inventors: Nele Mentens; Francesco Regazzoni; Edoardo Charbon - Web page: https://patentgrep.com/patent/US11309896B2 ## CPC - H03K 19/17768: for security - H03K 19/20: characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) - H04L 9/0618: {Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract A reconfigurable logic circuit comprises first, second and third switching circuits arranged for receiving first, second and third input bits, respectively, and each arranged for being configured in a mode wherein the corresponding input bit is passed on or in a mode; a first exclusive OR logic block operable on the outputs of the first, second and third switching circuits and arranged to output a sum bit; fourth, fifth and sixth switching circuits arranged for receiving a fourth, fifth and sixth input bits and arranged for being configured in a mode; first, second and third AND logic blocks, each arranged for receiving a different pair of the outputs of certain switching circuits; a second exclusive OR logic block operable on the outputs of certain AND logic blocks and arranged to produce a carry output bit. ## Claims ### Claim 1 A reconfigurable logic circuit comprising: a first switching circuit arranged for receiving only a first input bit and at least one first configuration bit, a second switching circuit arranged for receiving only a second input bit and at least one second configuration bit, and a third switching circuit arranged for receiving only a third input bit and at least one third configuration bit, said switching circuits arranged for being configured in a mode wherein the corresponding input bit is passed on or in a mode wherein a fixed logical zero or one is passed on, by setting the corresponding at least one configuration bit, a first exclusive OR logic block operable on the outputs of said first, second and third switching circuit and arranged to output a sum bit, a fourth switching circuit arranged for receiving only a fourth input bit and at least one fourth configuration bit, a fifth switching circuit arranged for receiving only a fifth input bit and at least one fifth configuration bit, and a sixth switching circuit arranged for receiving only a sixth input bit and at least one sixth configuration bit, and arranged for being configured in a mode wherein the corresponding input bit is passed on or in a mode wherein a fixed logical zero or one is passed on, by setting the corresponding at least one configuration bit, a first, second and third AND logic block, each arranged for receiving a different pair of outputs formed from the outputs of said fourth, fifth and sixth switching circuit, a second exclusive OR logic block operable on the outputs of said first, second and third AND logic block and arranged to produce a carry output bit, wherein the configuration bits are provided for programming the functionality of the logic circuit relative to the input bits. ### Claim 2 (depends on 1) The reconfigurable logic circuit as in claim 1, wherein at least one of said switching circuits is implemented with an AND logic block arranged for receiving the corresponding input bit and the corresponding at least one configuration bit and a OR logic block arranged for receiving the output of said AND logic block and a further configuration bit of the corresponding at least one configuration bit. ### Claim 3 (depends on 2) The reconfigurable logic circuit as in claim 2, wherein all switching circuits are implemented with an AND logic block and OR logic block. ### Claim 4 (depends on 3) The reconfigurable logic circuit as in claim 3, wherein said first and said fourth switching circuit have their further configuration bit set to a logical 0, said third and sixth switching circuit have their at least one configuration bit set to a logical 1 and said second and fourth switching circuit have their at least one configuration bit set to a logical 1 and their further configuration bit set to a logical 0. ### Claim 5 (depends on 2) The reconfigurable logic circuit as in claim 2, wherein the order of said AND logic block and said OR logic block is reversed, whereby the output of said OR logic block is arranged to be fed to said AND logic block. ### Claim 6 (depends on 1) The reconfigurable logic circuit as in claim 1, wherein said switching circuits are configurable for implementing one or more of the following functions: an addition modulo 2n, an addition modulo 2, or a substitution box. ### Claim 7 (depends on 1) The reconfigurable logic circuit as in claim 1, wherein said switching circuits are arranged to implement a quadratic function. ### Claim 8 (depends on 1) A slice comprising one or more reconfigurable logic circuits as in claim 1. ### Claim 9 (depends on 8) The slice as in claim 8, wherein each of said one or more reconfigurable logic circuits has a corresponding flipflop to which at least either said sum bit or said carry output bit can be applied. ### Claim 10 (depends on 8) The slice as in claim 8, further comprising multiplexing means. ### Claim 11 (depends on 8) The slice as in claim 8, comprising four reconfigurable logic circuits. ### Claim 12 A reconfigurable logic circuit comprising: a first switching circuit arranged for receiving a first input bit and at least one first configuration bit, a second switching circuit arranged for receiving a second input bit and at least one second configuration bit, and a third switching circuit arranged for receiving a third input bit and at least one third configuration bit, said switching circuits arranged for being configured in a mode wherein the corresponding input bit is passed on or in a mode wherein a fixed logical zero or one is passed on, by setting the corresponding at least one configuration bit, a first exclusive OR logic block operable on the outputs of said first, second and third switching circuit and arranged to output a sum bit, a fourth switching circuit arranged for receiving a fourth input bit and at least one fourth configuration bit, a fifth switching circuit arranged for receiving a fifth input bit and at least one fifth configuration bit, and a sixth switching circuit arranged for receiving a sixth input bit and at least one sixth configuration bit, and arranged for being configured in a mode wherein the corresponding input bit is passed on or in a mode wherein a fixed logical zero or one is passed on, by setting the corresponding at least one configuration bit, a first, second and third AND logic block, each arranged for receiving a different pair of outputs formed from the outputs of said fourth, fifth and sixth switching circuit, a second exclusive OR logic block operable on the outputs of said first, second and third AND logic block and arranged to produce a carry output bit; wherein each of the first, the second, the third, the fourth, the fifth and the sixth switching circuits are arranged for receiving only one input bit, wherein the configuration bits are provided for programming the functionality of the logic circuit relative to the input bits. ### Claim 13 A reconfigurable logic circuit comprising: a first switching circuit arranged for receiving a first input bit and at least one first configuration bit, a second switching circuit arranged for receiving a second input bit and at least one second configuration bit, and a third switching circuit arranged for receiving a third input bit and at least one third configuration bit, said switching circuits arranged for being configured in a mode wherein the corresponding input bit is passed on or in a mode wherein a fixed logical zero or one is passed on, by setting the corresponding at least one configuration bit, a first exclusive OR logic block operable on the outputs of said first, second and third switching circuit and arranged to output a sum bit, a fourth switching circuit arranged for receiving a fourth input bit and at least one fourth configuration bit, a fifth switching circuit arranged for receiving a fifth input bit and at least one fifth configuration bit, and a sixth switching circuit arranged for receiving a sixth input bit and at least one sixth configuration bit, and arranged for being configured in a mode wherein the corresponding input bit is passed on or in a mode wherein a fixed logical zero or one is passed on, by setting the corresponding at least one configuration bit, a first, second and third AND logic block, each arranged for receiving a different pair of outputs formed from the outputs of said fourth, fifth and sixth switching circuit, a second exclusive OR logic block operable on the outputs of said first, second and third AND logic block and arranged to produce a carry output bit; wherein a number of switching circuits in the reconfigurable logic circuit is equal to a number of input bits, wherein the configuration bits are provided for programming the functionality of the logic circuit relative to the input bits.