# US 11,309,895 B2 · Systems and methods for implementing a scalable system

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- Number: US 11,309,895 B2
- Document ID: US11309895B2
- Status: Granted
- Kind: B2
- Application number: 16/911,902
- Filed: 2020-06-25
- Published: 2020-12-10
- Granted: 2022-04-19
- Earliest claimed: 2018-04-12
- Assignees: Apple Inc.
- Applicants: Apple Inc.
- Inventors: Sanjay Dabral; Bahattin Kilic; Jie-Hua Zhao; Kunzhong Hu; Suk-Kyu Ryu
- Web page: https://patentgrep.com/patent/US11309895B2

## CPC

- H03K 19/1776: for memories
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- G06F 13/4022: {using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence)}
- G06F 15/7807: {System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package}
- H05K 1/0298: {Multilayer circuits}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/618: {the bridge chips being embedded in the package substrates, interposers or redistribution layers}
- H10W 70/635: {Through-vias}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 90/00: Package configurations
- H10W 70/63: Vias, e.g. via plugs
- H10W 70/692: Ceramics or glasses
- H10W 70/698: Semiconductor materials that are electrically insulating, e.g. undoped silicon
- H10W 72/07236: {Soldering or alloying}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/874: {On different surfaces}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 76/40: Fillings or auxiliary members in containers, e.g. centering rings (fillings or auxiliary members for thermal protection or control in containers or encapsulations H10W40/70)
- H10W 90/10: Configurations of laterally-adjacent chips
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Multi-chip systems and structures for modular scaling are described. In some embodiments an interfacing bar is utilized to couple adjacent chips. For example, a communication bar may utilized to coupled logic chips, and memory bar may be utilized to couple multiple memory chips to a logic chip.

## Claims

### Claim 1

A package on package structure:
a lower redistribution layer (RDL);
a first molding layer on the lower RDL;
an interfacing bar encapsulated in the first molding layer;
a second RDL over the first molding layer;
a first chip on top of the second RDL;
a package including a plurality of stacked chips on top of the second RDL;
wherein the first chip is a logic chip, and the plurality of stacked chips is a plurality of stacked memory chips; and
a second molding compound layer on the second RDL.

### Claim 2 (depends on 1)

The package on package structure of claim 1, further comprising a plurality of through vias extending through the first molding layer connecting the lower RDL and the second RDL.

### Claim 3 (depends on 1)

The package on package structure of claim 1, wherein the first chip is encapsulated in the second molding compound layer.

### Claim 4 (depends on 3)

The package on package structure of claim 3, further comprising a second plurality of through vias extending through the second molding compound layer and connected to the second RDL.

### Claim 5 (depends on 4)

The package on package structure of claim 4, wherein the package is bonded to the second plurality of through vias.

### Claim 6 (depends on 1)

The package on package structure of claim 1, wherein the interfacing bar comprises a routing layer extending a substantial portion of a longitudinal length of the interfacing bar.

### Claim 7 (depends on 6)

The package on package structure of claim 6, wherein:
the routing layer of the interfacing bar comprises a plurality of metal layers including a first wiring layer and a second wiring layer characterized by wider wiring than the first wiring layer.

### Claim 8 (depends on 7)

The package on package structure of claim 7, wherein:
a first memory chip of the plurality of stacked memory chips is electrically coupled with the logic chip through a first wire in the first wiring layer; and
a second memory chip of the plurality of stacked memory chips electrically coupled with the logic chip through a second wire in the second wiring layer.

### Claim 9 (depends on 8)

The package on package structure of claim 8, wherein:
and the second memory chip is located further away from the logic chip than the first memory chip is.

### Claim 10 (depends on 9)

The package on package structure of claim 9, wherein the first wiring layer is a lower wiring layer, and the second wiring layer is an upper wiring layer.

### Claim 11 (depends on 1)

The package on package structure of claim 1, wherein the interfacing bar comprises cache memory.

### Claim 12 (depends on 11)

The package on package structure of claim 11, wherein the plurality of stacked memory chips is a plurality of stacked dynamic random access memory (DRAM) chips.

### Claim 13 (depends on 1)

The package on package structure of claim 1, further comprising a plurality of solder bumps on a bottom side of the lower RDL.

### Claim 14 (depends on 1)

The package on package structure of claim 1, wherein the interfacing bar comprises a plurality of repeaters.

### Claim 15 (depends on 14)

The package on package structure of claim 14, wherein the plurality of repeaters is arranged along a longitudinal length of the interfacing bar.

### Claim 16 (depends on 14)

The package on package structure of claim 14, the interfacing bar comprises a routing layer extending a substantial portion of a longitudinal length of the interfacing bar, wherein the routing layer of the interfacing bar comprises a plurality of metal layers including a lower wiring layer and an upper wiring layer characterized by wider wiring than the lower wiring layer.

### Claim 17 (depends on 1)

The package on package structure of claim 1, wherein the interfacing bar includes a local processing element.

### Claim 18 (depends on 1)

The package on package structure of claim 1, wherein logic in the interfacing bar is to allocate memory such that more frequently used memory blocks in the package are closer to the logic chip, whereas less frequently used memory blocks in the package are further away.