# US 11,309,894 B2 · Method and system providing FPGA device identification via a set of embedded signature registers > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,309,894 B2 - Document ID: US11309894B2 - Status: Granted - Kind: B2 - Application number: 16/836,899 - Filed: 2020-03-31 - Published: 2021-09-30 - Granted: 2022-04-19 - Earliest claimed: 2020-03-31 - Assignees: GOWIN Semiconductor Corporation - Applicants: GOWIN Semiconductor Corporation - Inventors: Jinghui Zhu - Web page: https://patentgrep.com/patent/US11309894B2 ## CPC - H03K 19/17728: Reconfigurable logic blocks, e.g. lookup tables - H03K 19/1735: {by wiring, e.g. uncommitted logic arrays} - H03K 19/1737: {using multiplexers (H03K19/1738 takes precedence)} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A programmable integrated circuit (“PIC”) device includes configurable logic blocks (“LBs”), routing connections, and configuration memory for performing user defined programmed logic functions. Each configurable LB, in one example, includes a set of lookup tables (“LUTs”) and associated registers. The LUTs, for example, are configured to generate one or more output signals in accordance with a set of input signals. The registers are arranged so that each register corresponds to one LUT. In one embodiment, a group of registers, instead of assigning to a group of LUTs across multiple configurable LBs, is allocated or configured as embedded signature registers in PSD. For example, a first register which corresponds or physically situated in the vicinity of first LUT can be designated as an embedded signature register for storing a fixed value or signature information for facilitating device or IC identification. ## Claims ### Claim 1 A programmable integrated circuit (“PIC”) device containing configurable logic blocks (“LBs”), an array of routing connections, and a configuration memory for performing programmed logic functions, each of the configurable LB s comprising: a plurality of lookup tables (“LUTs”) configured to generate one or more output signals in accordance with a set of input signals; and a plurality of registers coupled to the plurality of LUTs and arranged so that one of the plurality of registers corresponding to one of the plurality of LUTs, wherein a first register of the plurality of registers corresponding to a first LUT of the plurality of LUTs is designated for storing a fixed value for facilitating device identification, wherein a second register of the plurality of registers corresponding to a second LUT of the plurality of LUTs is configured to store a second output signal generated by the second LUT, wherein the fixed value is read during a bitstream readback process to verify device identity. ### Claim 2 (depends on 1) The device of claim 1, wherein a third register of the plurality of registers corresponding to a third LUT of the plurality of LUTs is designated for storing a fixed value for facilitating device identification. ### Claim 3 (depends on 2) The device of claim 2, wherein a fourth register of the plurality of registers corresponding to a fourth LUT of the plurality of LUTs is configured to store a fourth output signal generated by the fourth LUT. ### Claim 4 (depends on 3) The device of claim 3, wherein a fifth register of the plurality of registers corresponding to a fifth LUT of the plurality of LUTs is configured to store a fifth output signal generated by the fifth LUT; and wherein a sixth register of the plurality of registers corresponding to a sixth LUT of the plurality of LUTs is configured to store a sixth output signal generated by the sixth LUT. ### Claim 5 (depends on 4) The device of claim 4, wherein a seventh register of the plurality of registers corresponding to a seventh LUT of the plurality of LUTs is configured to store a seventh output signal generated by the seventh LUT; and wherein an eighth register of the plurality of registers corresponding to an eighth LUT of the plurality of LUTs is configured to store an eighth output signal generated by the eighth LUT. ### Claim 6 (depends on 1) The device of claim 1, wherein the fixed value of the first register of the plurality of registers is forced by a local controller during an IC identification process. ### Claim 7 (depends on 1) The device of claim 1, further comprising a plurality of multiplexers coupled to the plurality of LUTs and configured to provide internal routing between the plurality of LUTs and the plurality of registers. ### Claim 8 (depends on 1) The device of claim 1, wherein a third register of the plurality of registers corresponding to a third LUT of the plurality of LUTs is designated for storing signature information for facilitating device identification; and wherein a fourth register of the plurality of registers corresponding to a fourth LUT of the plurality of LUTs is designated for storing signature information for facilitating device identification. ### Claim 9 (depends on 1) A system configured to provide various digital processing functions and network communications comprising the device of claim 1. ### Claim 10 A programmable integrated circuit (“PIC”) device containing configurable logic blocks (“LBs”), an array of routing connections, and a configuration memory for performing programmed logic functions, each of the configurable LBs comprising: a plurality of lookup tables (“LUTs”) configured to generate one or more output signals in accordance with a set of input signals; and a plurality of registers coupled to the plurality of LUTs and arranged so that one of the plurality of registers corresponding to one of the plurality of LUTs, wherein a first register of the plurality of registers corresponding to a first LUT of the plurality of LUTs is designated for storing a fixed value for facilitating device identification, wherein a second register of the plurality of registers corresponding to a second LUT of the plurality of LUTs is configured to store a second output signal generated by the second LUT, wherein the fixed value is forced by a local controller during an IC identification process. ### Claim 11 (depends on 10) The device of claim 10, wherein a third register of the plurality of registers corresponding to a third LUT of the plurality of LUTs is designated for storing a fixed value for facilitating device identification. ### Claim 12 (depends on 11) The device of claim 11, wherein a fourth register of the plurality of registers corresponding to a fourth LUT of the plurality of LUTs is configured to store a fourth output signal generated by the fourth LUT. ### Claim 13 (depends on 12) The device of claim 12, wherein a fifth register of the plurality of registers corresponding to a fifth LUT of the plurality of LUTs is configured to store a fifth output signal generated by the fifth LUT; and wherein a sixth register of the plurality of registers corresponding to a sixth LUT of the plurality of LUTs is configured to store a sixth output signal generated by the sixth LUT. ### Claim 14 (depends on 13) The device of claim 13, wherein a seventh register of the plurality of registers corresponding to a seventh LUT of the plurality of LUTs is configured to store a seventh output signal generated by the seventh LUT. ### Claim 15 (depends on 14) The device of claim 14, wherein an eighth register of the plurality of registers corresponding to an eighth LUT of the plurality of LUTs is configured to store an eighth output signal generated by the eighth LUT. ### Claim 16 (depends on 10) The device of claim 10, wherein the fixed value of the first register of the plurality of registers is read during a bitstream readback process to verify device identity. ### Claim 17 (depends on 10) The device of claim 10, further comprising a plurality of multiplexers coupled to the plurality of LUTs and configured to provide internal routing between the plurality of LUTs and the plurality of registers. ### Claim 18 (depends on 10) The device of claim 10, wherein a third register of the plurality of registers corresponding to a third LUT of the plurality of LUTs is designated for storing signature information for facilitating device identification; and wherein a fourth register of the plurality of registers corresponding to a fourth LUT of the plurality of LUTs is designated for storing signature information for facilitating device identification. ### Claim 19 (depends on 10) A system configured to provide various digital processing functions and network communications comprising the device of claim 10.