# US 11,309,892 B2 · Data bus signal conditioner and level shifter

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 11,309,892 B2
- Document ID: US11309892B2
- Status: Granted
- Kind: B2
- Application number: 17/174,119
- Filed: 2021-02-11
- Published: 2021-08-12
- Granted: 2022-04-19
- Earliest claimed: 2020-02-12
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Win Naing Maung; Bharath Kumar Singareddy; Soumi Paul; Mayank Garg; Suzanne Mary Vining
- Web page: https://patentgrep.com/patent/US11309892B2

## CPC

- G06F 13/4072: {Drivers or receivers (G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002)}
- H03K 19/018521: {of complementary type, e.g. CMOS}
- G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)}
- H03K 19/0175: Coupling arrangements; Interface arrangements (interface arrangements for digital computers G06F3/00, G06F13/00)
- H04B 3/36: Repeater circuits (H04B3/58 takes precedence)
- H04L 7/0041: {Delay of data signal}
- H04L 25/0272: {Arrangements for coupling to multiple lines, e.g. for differential transmission}
- H04L 7/0079: {Receiver details}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H04B: TRANSMISSION
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A circuit includes signal conditioner circuitry, level shifter circuitry, and state detector and controller circuitry coupled between the signal conditioner circuitry and the level shifter circuitry. The state detector and controller circuitry includes receiver circuitry and a finite state machine coupled to the receiver circuitry. The finite state machine is configured to detect a first data rate from signals, control operation of the signal conditioner circuitry responsive to detecting the first data rate, and control operation of the level shifter circuitry during a second data rate.

## Claims

### Claim 1

A circuit comprising:
signal conditioner circuitry;
level shifter circuitry; and
state detector and controller circuitry coupled between the signal conditioner circuitry and the level shifter circuitry and including:
receiver circuitry; and
a finite state machine coupled to the receiver circuitry and configured to:
detect a first data rate from signals;
control operation of the signal conditioner circuitry responsive to detecting the first data rate; and
control operation of the level shifter circuitry during a second data rate.

### Claim 2 (depends on 1)

The circuit of claim 1, wherein the first data rate is a high-speed data rate, and the second data rate is a low-speed data rate or a full-speed data rate.

### Claim 3 (depends on 2)

The circuit of claim 2, wherein:
the high-speed data rate is 480 megabits per second (Mb/s);
the full-speed data rate is 12 Mb/s; and
the low-speed data rate is 1.5 Mb/s.

### Claim 4 (depends on 1)

The circuit of claim 1, wherein the finite state machine is a first finite state machine, the circuit further comprising low power state detection circuitry including:
a differential receiver;
a clock and data recovery (CDR) circuit coupled to the differential receiver; and
a second finite state machine coupled to the differential receiver and the CDR circuit and configured to detect a low power state from the signals using a clock signal generated by the CDR circuit.

### Claim 5 (depends on 4)

The circuit of claim 4, wherein:
the CDR circuit is configured to generate the clock signal using a synchronization pattern of a packet communicated in the signals; and
the second finite state machine is configured to detect a link power management LPM-L1 state using a packet identifier of the packet.

### Claim 6 (depends on 1)

The circuit of claim 1, wherein the signal conditioner circuitry is configured to boost edges of the signals.

### Claim 7

A system comprising:
a first integrated circuit;
a second integrated circuit; and
an intermediary circuit coupled between the first and second integrated circuits, and including:
first switches;
signal conditioner circuitry configured to boost edges of signals during a state in which the first switches are closed;
second switches;
level shifter circuitry operable during a state in which the second switches are closed; and
state detector and controller circuitry including:
receiver circuitry; and
a finite state machine coupled to the receiver circuitry and configured to:
detect, from signals received at the receiver circuitry, a first data rate;
close the first switches responsive to detecting the first data rate; and
close the second switches during a second data rate.

### Claim 8 (depends on 7)

The system of claim 7, wherein the first integrated circuit is a first embedded Universal Serial Bus (eUSB2) device and the second integrated circuit is a second eUSB2 device.

### Claim 9 (depends on 7)

The system of claim 7, wherein the first data rate is a high-speed data rate, and the second data rate is a low-speed data rate or a full-speed data rate.

### Claim 10 (depends on 7)

The system of claim 7, wherein the finite state machine is a first finite state machine, the circuit further comprising low power state detection circuitry including:
a differential receiver;
a clock and data recovery (CDR) circuit coupled to the differential receiver; and
a second finite state machine coupled to the differential receiver and the CDR circuit and configured to detect a link power management LPM-L1 (L1) state from the signals using a clock signal generated by the CDR circuit.

### Claim 11 (depends on 10)

The system of claim 10, wherein:
the CDR circuit is configured to generate the clock signal using a synchronization pattern of a packet communicated in the signals; and
the second finite state machine is configured to detect the L1 state using a packet identifier of the packet.

### Claim 12

A method comprising:
receiving signals;
detecting, from the signals, a first data rate;
operating signal conditioner circuitry responsive to detecting the first data rate, for boosting edges of the signals; and
operating level shifter circuitry during a second data rate, for shifting a voltage level of the signals from a first voltage level to a second voltage level.

### Claim 13 (depends on 12)

The method of claim 12, wherein the first data rate is a high-speed data rate, and the second data rate is a low-speed data rate or a full-speed data rate.

### Claim 14 (depends on 12)

The method of claim 12, further comprising operating low power mode detection circuitry responsive to detecting the second data rate, for detecting a link power management LPM-L1 (L1) state from the signals.

### Claim 15 (depends on 14)

The method of claim 14, wherein operating the low power mode detection circuitry includes generating clock signals using a respective synchronization (SYNC) pattern within packets communicated in the signals.

### Claim 16 (depends on 15)

The method of claim 15, wherein detecting the L1 state includes:
providing the clock signals to a finite state machine; and
detecting an EXT packet identifier (PID), a SUB PID, and an ACK PID in a succession of the packets, by the finite state machine, using the clock signals.

### Claim 17 (depends on 12)

The method of claim 12, further comprising detecting an embedded Universal Serial Bus single ended one (ESE1) state from the signals.

### Claim 18

An intermediary circuit adapted to be coupled between first and second communication devices using first and second conductors and operable to facilitate communications between the first and second communication devices, the intermediary circuit comprising:
a state detector and controller circuit having first and second outputs and adapted to be coupled to the first and second conductors;
a signal conditioning circuit coupled to the first output and adapted to be coupled to the first and second conductors; and
a level shifter coupled to the second output and adapted to be coupled to the first and second conductors.

### Claim 19 (depends on 18)

The intermediary circuit of claim 18, wherein the state detector and controller circuit is configured to:
detect a state of communication;
enable the signal conditioning circuit responsive to detecting a first state of communication; and
enable the level shifter during a second state of communication.

### Claim 20 (depends on 19)

The intermediary circuit of claim 19, wherein the first state of communication is a high-speed data rate, and the second state of communication is a low-speed data rate or a full-speed data rate.

### Claim 21 (depends on 18)

The intermediary circuit of claim 18, wherein the signal conditioning circuit is configured to boost edges of signals on the first and second conductors.

### Claim 22 (depends on 18)

The intermediary circuit of claim 18, wherein the level shifter is configured to shift voltage levels of signals on the first and second conductors.