# US 11,309,884 B1 · Switching circuits having drain connected ferrite beads

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- Number: US 11,309,884 B1
- Document ID: US11309884B1
- Status: Granted
- Kind: B1
- Application number: 17/138,101
- Filed: 2020-12-30
- Granted: 2022-04-19
- Earliest claimed: 2017-11-21
- Assignees: Transphorm Technology, Inc.
- Applicants: Transphorm Technology, Inc.
- Inventors: Jason Cuadra; Yifeng Wu; Zhan Wang
- Web page: https://patentgrep.com/patent/US11309884B1

## CPC

- H03K 17/162: {without feedback from the output circuit to the control circuit}
- H03K 17/04106: {in field-effect transistor switches (H03K17/0412, H03K17/0416 take precedence)}
- H03K 17/102: {in field-effect transistor switches}
- H03K 17/122: {in field-effect transistor switches}
- H03K 17/6871: {the output circuit comprising more than one controlled field-effect transistor}
- H03K 17/6874: {in a symmetrical configuration}
- H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
- H10W 70/481: {for devices being provided for in groups H10D8/00 - H10D48/00}
- H10W 90/00: Package configurations
- H03K 2017/6875: {using self-conductive, depletion FETs}
- H03K 2217/0063: High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load
- H03K 2217/0072: Low side switches, i.e. the lower potential [DC] or neutral wire [AC] being directly connected to the switch and not via the load
- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 90/753: {between laterally-adjacent chips}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A circuit includes an electronic component package that comprises a first lead, a second lead, and a third lead; and a III-N transistor encased in the electronic component package, the III-N transistor including a drain, a gate, and a source, where the source is coupled to the first lead, the gate is coupled to the second lead, and the drain is coupled to the third lead. The circuit includes a high voltage node and a resistor, the resistor having a first terminal coupled to the high voltage node and a second terminal coupled to the third lead. The circuit further includes a ferrite bead connected in parallel to the resistor and coupled between the third lead and the high voltage node. When switching, the deleterious effects of a parasitic inductance of the circuit's power loop are mitigated by the ferrite bead and the resistor.

## Claims

### Claim 1

A circuit comprising:
a high side III-N transistor comprising:
a high side drain coupled to a high voltage node; and
a high side source coupled to a load node;
a low side III-N transistor comprising:
a low side drain coupled to the load node; and
a low side source coupled to a ground node;
a first ferrite bead coupled between the high side drain and the high voltage node and a second ferrite bead coupled between the low side source and the ground node; and
a resistor with a first terminal and a second terminal, wherein the first terminal of the resistor is coupled to the high side drain and the second terminal is coupled to the high-voltage node.

### Claim 2 (depends on 1)

The circuit of claim 1, further comprising a second resistor with a third terminal and a fourth terminal, wherein the third terminal is coupled to the low side source and the fourth terminal is coupled to the ground node.

### Claim 3 (depends on 1)

The circuit of claim 1, wherein the low side III-N transistor and/or the high side III-N transistor is a hybrid device comprising a depletion mode III-N transistor and an enhancement mode transistor.

### Claim 4 (depends on 1)

The circuit of claim 1, wherein the high side III-N transistor is implemented as two or more III-N transistors connected in parallel, and the low side III-N transistor is implemented as two or more III-N transistors connected in parallel.

### Claim 5 (depends on 4)

The circuit of claim 4, wherein each of the high side III-N transistors connected in parallel are coupled to their own respective additional ferrite beads between their high side drain and the high voltage node, and each of the low side III-N transistors connected in parallel are coupled to their own respective additional ferrite beads between their low side source and the ground node.

### Claim 6 (depends on 1)

The circuit of claim 1, wherein the high side III-N transistor is encased in an electronic component package, the electronic component package further comprising a conductive structural base, wherein the high side III-N transistor is a lateral III-N transistor, and the high side drain is electrically connected to the conductive structural base of the electronic component package.

### Claim 7 (depends on 1)

The circuit of claim 1, wherein the low side III-N transistor is encased in an electronic component package, the electronic component package further comprising a conductive structural base, wherein the low side III-N transistor is a lateral III-N transistor, and the low side source is electrically connected to the conductive structural base of the electronic component package.

### Claim 8 (depends on 1)

The circuit of claim 1, wherein the first ferrite bead and/or the second ferrite bead have an effective resistance between 100 and 500 at 100 MHz and a DC resistance of less than 10 mΩ.

### Claim 9 (depends on 1)

The circuit of claim 1, wherein a resistance of the resistor is less than an effective resistance of the ferrite bead at 100 MHz and greater than a DC resistance of the ferrite bead.

### Claim 10 (depends on 1)

The circuit of claim 1, wherein the first ferrite bead and/or the second ferrite bead are surface-mounted device (SMD) ferrite beads.