# US 11,309,876 B2 · Digitally programmable analog duty-cycle correction circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,309,876 B2 - Document ID: US11309876B2 - Status: Granted - Kind: B2 - Application number: 16/686,731 - Filed: 2019-11-18 - Published: 2021-05-20 - Granted: 2022-04-19 - Earliest claimed: 2019-11-18 - Assignees: MACOM Technology Solutions Holdings, Inc. - Applicants: MACOM Technology Solutions Holdings, Inc. - Inventors: Naga Rajesh Doppalapudi; Mahmoud Reza Ahmadi; Echere Iroaga - Web page: https://patentgrep.com/patent/US11309876B2 ## CPC - H03K 5/1565: {the output pulses having a constant duty cycle} - H03M 9/00: Parallel/series conversion or vice versa (digital stores in which the information is moved stepwise per se G11C19/00) - G06F 1/08: Clock generators with changeable or programmable clock frequency - G06F 1/10: Distribution of clock signals {, e.g. skew} - H03F 3/45183: {Long tailed pairs (H03F3/4521, H03F3/45237 take precedence)} - H03F 3/45748: {by using a feedback circuit} - H03K 7/08: Duration or width modulation {; Duty cycle modulation} - H03M 1/66: Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) - H04J 3/062: {Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers (pulse-stuffing H04J3/07; asynchronous-synchronous conversion H04L5/24; speed conversion H04L25/05; speed conversion in computers G06F5/06)} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03F: AMPLIFIERS - H04J: MULTIPLEX COMMUNICATION (transmission in general H04B; peculiar to transmission of digital information H04L5/00; systems for the simultaneous or sequential transmission of more than one television signal H04N7/08; in exchanges H04Q11/00; stereophonic systems H04S) ## Abstract Various aspects provide for a digitally programmable analog duty-cycle correction circuit. For example, a system includes a duty-cycle correction circuit and a duty-cycle distortion detector circuit. The duty-cycle correction circuit adjusts a clock associated with the transmitter. The duty-cycle distortion detector circuit facilitates digital control of a duty-cycle of the clock associated with the duty-cycle correction circuit based on duty-cycle distortion error associated with output of the transmitter. ## Claims ### Claim 1 A system for reducing error associated with a transmitter, comprising: a duty-cycle correction circuit configured to adjust a clock associated with the transmitter; a duty-cycle distortion detector circuit configured to facilitate digital control of a duty-cycle of the clock associated with the duty-cycle correction circuit based on a duty-cycle distortion error associated with output of the transmitter; an accumulator component configured to receive and accumulate bits of information that are indicative of the duty-cycle distortion error, and convert the bits of information to a multiple-bit duty-cycle distortion error code word that corresponds to the duty-cycle distortion error; and a core component configured to receive a first input data signal having a first defined input data bit pattern, a second input data signal having a second defined input data bit pattern, a first clock signal associated with the clock, and a second clock signal associated with the clock, wherein the output comprises a first output data signal and a second output data signal generated based on the first input data signal, the second input data signal, the first clock signal, and the second clock signal, wherein the duty-cycle distortion detector circuit is configured to determine a first average value of the first output data signal and a second average value of the second output data signal, determine a differential average value of the first average value and the second average value based on a comparison of the first average value to the second average value, and determine the duty-cycle distortion error, based on the differential average value, wherein the bits of information comprise the differential average value, wherein the multiple-bit duty-cycle distortion error code word is determined based on the differential average value, wherein an offset signal corresponding to an offset value is generated based on the multiple-bit duty-cycle distortion error code word indicative of the duty-cycle distortion error, the offset signal comprising a bias current that corresponds to the offset value and is applied to drains of transistors, comprising a differential pair of transistors, of an amplifier of the duty-cycle correction circuit, and, to reduce the duty-cycle distortion error, the duty-cycle correction circuit is configured to adjust the clock to adjust the first clock signal and the second clock signal applied to the core component based on the bias current applied to the drains of the transistors of the amplifier of the duty-cycle correction circuit; a set of switches associated with a gate of a transistor; and a current source device configured to facilitate applying the offset signal to the amplifier of the duty-cycle correction circuit: at a first time, control a switch of the set of switches to place the switch in a first state to provide a bias voltage to the gate of the transistor to switch the transistor to an on state; and at a second time, control the switch to place the switch in a second state to discontinue providing the bias voltage to the gate of the transistor to switch the transistor to an off state. ### Claim 2 (depends on 1) The system of claim 1, wherein the duty-cycle distortion detector circuit comprises the accumulator component, wherein the duty-cycle distortion detector circuit is configured to generate a digital code associated with the duty-cycle distortion error, and the digital code is generated based on error information indicative of the duty-cycle distortion error, and wherein the digital code comprises the multiple-bit duty-cycle distortion error code word. ### Claim 3 (depends on 1) The system of claim 1, wherein the duty-cycle distortion detector circuit comprises the accumulator component, wherein the duty-cycle distortion detector circuit is configured to provide a digital code associated with the duty-cycle distortion error to a digital logic circuit that generates a defined bit pattern, and the digital code is generated based on error information indicative of the duty-cycle distortion error, and wherein the digital code comprises the multiple-bit duty-cycle distortion error code word. ### Claim 4 (depends on 1) The system of claim 1, further comprising a digital logic circuit configured for providing a defined bit pattern associated with the duty-cycle distortion error to a digital-to-analog converter that digitally controls the duty-cycle of the clock, wherein the defined bit pattern corresponds to error information indicative of the duty-cycle distortion error. ### Claim 5 (depends on 1) The system of claim 1, further comprising a digital-to-analog converter configured for generating the offset signal corresponding to the offset value for the amplifier of the duty-cycle correction circuit based on the duty-cycle distortion error. ### Claim 6 (depends on 1) The system of claim 1, wherein the duty-cycle distortion detector circuit is configured to measure the duty-cycle distortion error associated with the transmitter as a function of the first output data signal and the second output data signal. ### Claim 7 (depends on 6) The system of claim 6, wherein the duty-cycle distortion detector circuit comprises the accumulator component, wherein the duty-cycle distortion detector circuit is configured to compare the first average value of the first output data signal and the second average value of the second output data signal to facilitate generation of a digital code associated with the duty-cycle distortion error, and the digital code is generated based on error information indicative of the duty-cycle distortion error, and wherein the digital code comprises the multiple-bit duty-cycle distortion error code word. ### Claim 8 (depends on 6) The system of claim 6, wherein the duty-cycle distortion detector circuit is configured to facilitate the digital control of the duty-cycle of the clock based on the comparison between the first average value of the first output data signal and the second average value of the second output data signal. ### Claim 9 A system for digitally controlling an analog duty-cycle correction circuit, comprising: a transmitter configured to generate output based on a clock associated with the analog duty-cycle correction circuit; a duty-cycle distortion detector circuit configured to facilitate digital control of a duty-cycle of the clock associated with the analog duty-cycle correction circuit based on a duty-cycle distortion error associated with the output of the transmitter; an accumulator component configured to receive and accumulate bits of data that are representative of the duty-cycle distortion error, and convert the bits of data to a multiple-bit duty-cycle distortion error code word that is indicative of the duty-cycle distortion error; a core component configured to receive a first input data stream having a first defined data pattern, a second input data stream having a second defined data pattern, a first clock signal associated with the clock, and a second clock signal associated with the clock, wherein the output comprises a first output data stream and a second output data stream generated based on the first input data stream, the second input data stream, the first clock signal, and the second clock signal, the duty-cycle distortion detector circuit is configured to determine a first average value of the first output data stream and a second average value of the second output data stream, determine a differential average value of the first average value and the second average value, and determine the duty-cycle distortion error, based on the differential average value, wherein the bits of data comprise the differential average value, wherein the multiple-bit duty-cycle distortion error code word is generated based on the differential average value, and wherein an offset value is determined based on the multiple-bit duty-cycle distortion error code word associated with the duty-cycle distortion error, and wherein a bias current corresponding to the offset value is generated, based on the multiple-bit duty-cycle distortion error code word, and is applied to drains of transistors of an amplifier of the analog duty-cycle correction circuit to control the analog duty-cycle correction circuit to modify the first clock signal and the second clock signal, based on the offset value, to mitigate the duty-cycle distortion error; a set of switches associated with a gate of a transistor; and a current source device configured to facilitate applying the offset signal to the amplifier of the analog duty-cycle correction circuit: at a first time, control a switch of the set of switches to place the switch in a first state to provide a bias voltage to the gate of the transistor to switch the transistor to an on state; and at a second time, control the switch to place the switch in a second state to discontinue providing the bias voltage to the gate of the transistor to switch the transistor to an off state. ### Claim 10 (depends on 9) The system of claim 9, wherein the duty-cycle distortion detector circuit comprises the accumulator component, wherein the duty-cycle distortion detector circuit is configured to generate a digital code associated with the duty-cycle distortion error, wherein the accumulator component is configured to generate the digital code based on error data associated with the duty-cycle distortion error, and wherein the digital code comprises the multiple-bit duty-cycle distortion error code word. ### Claim 11 (depends on 9) The system of claim 9, wherein the duty-cycle distortion detector circuit comprises the accumulator component, wherein the duty-cycle distortion detector circuit is configured to provide a digital code associated with the duty-cycle distortion error to a digital logic circuit that generates a defined bit pattern, wherein the accumulator component is configured to generate the digital code based on error data associated with the duty-cycle distortion error, and wherein the digital code comprises the multiple-bit duty-cycle distortion error code word. ### Claim 12 (depends on 9) The system of claim 9, further comprising a digital logic circuit configured for providing a defined bit pattern associated with the duty-cycle distortion error to a digital-to-analog converter that digitally controls the duty-cycle of the clock, wherein the defined bit pattern is generated based on error data associated with the duty-cycle distortion error. ### Claim 13 (depends on 9) The system of claim 9, further comprising a digital-to-analog converter configured for generating the offset value for the amplifier of the analog duty-cycle correction circuit based on the duty-cycle distortion error. ### Claim 14 (depends on 9) The system of claim 9, wherein the duty-cycle distortion detector circuit is configured to measure the duty-cycle distortion error associated with the transmitter based on the first output data stream and the second output data stream. ### Claim 15 (depends on 14) The system of claim 14, wherein the duty-cycle distortion detector circuit comprises the accumulator component, wherein the duty-cycle distortion detector circuit is configured to compare the first average value of the first output data stream and the second average value of the second output data stream to facilitate generation of a digital code associated with the duty-cycle distortion error, wherein the accumulator component is configured to generate the digital code based on error data associated with the duty-cycle distortion error, and wherein the digital code comprises the multiple-bit duty-cycle distortion error code word. ### Claim 16 (depends on 14) The system of claim 14, wherein the duty-cycle distortion detector circuit is configured to facilitate the digital control of the duty-cycle of the clock based on the comparison between the first average value of the first output data stream and the second average value of the second output data stream. ### Claim 17 A method, comprising: generating output, comprising a first output data signal and a second output data signal, of a transmitter, based on a first input data signal having a first defined input data bit pattern, a second input data signal having a second defined input data bit pattern, and a first clock signal and a second clock signal associated with a clock associated with an analog duty-cycle correction circuit; determining a first average value of the first output data signal and a second average value of the second output data signal; determining a differential average value of the first average value and the second average value based on comparing the first average value to the second average value; determining a duty-cycle distortion error associated with the output of the transmitter based on the differential average value; accumulating bits of data that are indicative of the duty-cycle distortion error, wherein the bits of data comprise the differential average value; generating a digital multiple-bit duty-cycle distortion error code word associated with the duty-cycle distortion error based on the differential average value; based on the digital multiple-bit duty-cycle distortion error code word associated with the duty-cycle distortion error, generating an offset signal comprising a bias current corresponding to an offset value that is applied to drains of transistors of an amplifier of the analog duty-cycle correction circuit to control a duty-cycle of the clock associated with the analog duty-cycle correction circuit to control the first clock signal and the second clock signal; associating a set of switches with a gate of a transistor; and to facilitate applying the offset signal to the amplifier of the analog duty-cycle correction circuit: at a first time, controlling a switch of the set of switches to place the switch in a first state to provide a bias voltage to the gate of the transistor to switch the transistor to an on state; and at a second time, controlling the switch to place the switch in a second state to discontinue providing the bias voltage to the gate of the transistor to switch the transistor to an off state. ### Claim 18 (depends on 17) The method of claim 17, wherein the generating of the offset signal comprises generating the offset signal using a digital-to-analog converter that provides the bias current associated with the duty-cycle distortion error to the drains of the transistors of the amplifier of the analog duty-cycle correction circuit, the bias current being determined based on the digital multiple-bit duty-cycle distortion error code word. ### Claim 19 (depends on 17) The method of claim 17, further comprising: providing a defined bit pattern associated with the duty-cycle distortion error to a digital-to-analog converter, wherein the defined bit pattern is generated based on the digital multiple-bit duty-cycle distortion error code word.