Sequential elements with programmable feedback to program leakage in ASICs
AssigneeBitmain Development Inc.
InventorsChristos Vezyrtzis, Peter Holm, Steve Beccue
Life of this patent
Estimating the term…
Abstract
Power dissipation of sequential static latch, implemented in CMOS, may be reduced by removing clocked elements from the circuit. One way to do this may be to replace a clocked digital feedback path with an analog programmable feedback path. An analog programmable feedback path, such as disclosed, may, for example, provide a constant, non-clocked bias by providing constant bias voltages to transistors in the feedback path such that they function as analog devices rather than digital switches. This bias may be adjusted, e.g., to reflect the circuit's operating environment.
Claims6
A latched sequential circuit element, comprising:
- a front end comprising a data input, a clock input (CPP), and a negative clock input (CPN) and configured to have an output connected to an internal node;
- a first inverter with an input connected to the internal node and an output connected to an output node;
- and
- an analog programmable feedback path comprising
- a second inverter with an input connected to the internal node and an output connected to a feedback node, and
- an analog-biased inverter with an input connected to the feedback node and an output connected to the internal node;
- wherein:
- the analog-biased inverter comprises, in series, a first nMOS transistor, a second nMOS transistor, a first pMOS transistor, and a second pMOS transistor, each transistor having its own respective gate, source, and drain;
- the gate of the first nMOS transistor is connected to the feedback node, the source of the first nMOS transistor is connected to VSS, and the drain of the first nMOS transistor is connected to the source of the second nMOS transistor;
- the gate of the second nMOS transistor is held to a first analog bias voltage VBFBN, and the drain of the second nMOS transistor is connected to the internal node;
- the gate of the first pMOS transistor is held to a second analog bias voltage VBFBP, the drain of the first pMOS transistor is connected to the internal node, and the source of the first pMOS transistor is connected to the drain of the second pMOS transistor;
- and
- the gate of the second pMOS transistor is connected to the feedback node, and the source of the second pMOS transistor is connected to VDD.
Dependencies are inferred from the claim text.