# US 11,309,852 B2 · Power amplifier and compound semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,309,852 B2 - Document ID: US11309852B2 - Status: Granted - Kind: B2 - Application number: 16/995,902 - Filed: 2020-08-18 - Published: 2020-12-03 - Granted: 2022-04-19 - Earliest claimed: 2017-11-20 - Assignees: Murata Manufacturing Co., Ltd. - Applicants: Murata Manufacturing Co., Ltd. - Inventors: Isao Obu; Satoshi Tanaka; Takayuki Tsutsui; Yasunari Umemoto - Web page: https://patentgrep.com/patent/US11309852B2 ## CPC - H03F 3/211: {using a combination of several amplifiers (H03F3/60 takes precedence)} - H03F 1/0211: {with control of the supply voltage or current} - H03F 1/56: Modifications of input or output impedances, not otherwise provided for - H03F 3/19: with semiconductor devices only - H10D 84/01: Manufacture or treatment - H10D 84/0107: {Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs} - H10D 84/05: using Group III-V technology - H10D 84/401: {Combinations of FETs or IGBTs with BJTs} - H03F 2200/222: A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier - H03F 2200/318: A matching circuit being used as coupling element between two amplifying stages - H03F 2200/387: A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier - H03F 2200/451: the amplifier being a radio frequency amplifier - H03F: AMPLIFIERS - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A power amplifier includes initial-stage and output-stage amplifier circuits, and initial-stage and output-stage bias circuits. The initial-stage amplifier circuit includes a first high electron mobility transistor having a source electrically connected to a reference potential, and a gate to which a radio-frequency input signal is inputted, and a first heterojunction bipolar transistor having an emitter electrically connected to a drain of the first high electron mobility transistor, a base electrically connected to the reference potential in an alternate-current fashion, and a collector to which direct-current power is supplied and from which a radio-frequency signal is outputted. The output-stage amplifier circuit includes a second heterojunction bipolar transistor having an emitter electrically connected to the reference potential, a base to which the radio-frequency signal outputted from the first heterojunction bipolar transistor is inputted, and a collector to which direct-current power is supplied and from which a radio-frequency output signal is outputted. ## Claims ### Claim 1 A power amplifier comprising: an initial-stage amplifier circuit comprising: a first high electron mobility transistor having a source electrically connected to a reference potential, and a gate to which a radio-frequency input signal is input, and a first heterojunction bipolar transistor having an emitter electrically connected to a drain of the first high electron mobility transistor, a base electrically connected to the reference potential in an alternate-current fashion via a first node, and a collector to which direct-current power is supplied and from which a radio-frequency signal is output; a second-stage amplifier circuit comprising: a third high electron mobility transistor having a source electrically connected to a reference potential, and a gate to which the radio-frequency signal output from the first heterojunction bipolar transistor is input, and a fifth heterojunction bipolar transistor having an emitter electrically connected to a drain of the third high electron mobility transistor, a base electrically connected to the reference potential in an alternate-current fashion via a third node, and a collector to which direct-current power is supplied and from which a radio-frequency signal is output; an output-stage amplifier circuit comprising: a second heterojunction bipolar transistor having an emitter electrically connected to the reference potential, a base to which the radio-frequency signal output from the fifth heterojunction bipolar transistor is input, and a collector to which direct-current power is supplied and from which a radio-frequency output signal is output; an initial-stage bias circuit configured to output a first bias voltage to the gate of the first high electron mobility transistor and a second bias voltage to the base of the first heterojunction bipolar transistor, the initial-stage bias circuit comprising: a third heterojunction bipolar transistor having a base electrically connected to the first node, a fourth heterojunction bipolar transistor having a base electrically connected to the first node, and an emitter electrically connected to a second node, the second node being electrically connected to the gate of the first high electron mobility transistor, and a capacitor connected between the first node and the reference potential; a second-stage bias circuit configured to output a fourth bias voltage to the gate of the third high electron mobility transistor and a fifth bias voltage to the base of the fifth heterojunction bipolar transistor, the second-stage bias circuit comprising: a sixth heterojunction bipolar transistor having a base electrically connected to the third node, a seventh heterojunction bipolar transistor having a base electrically connected to the third node, and an emitter electrically connected to a fourth node, the fourth node being electrically connected to the gate of the third high electron mobility transistor, and a capacitor connected between the third node and the reference potential; and an output-stage bias circuit configured to output a third bias voltage to the base of the second heterojunction bipolar transistor. ### Claim 2 (depends on 1) The power amplifier according to claim 1, wherein the first high electron mobility transistor is a depletion type high electron mobility transistor. ### Claim 3 (depends on 1) The power amplifier according to claim 1, wherein the third high electron mobility transistor is a depletion type high electron mobility transistor. ### Claim 4 (depends on 1) The power amplifier according to claim 1, wherein the initial-stage bias circuit comprises: the first node to which a reference current is supplied, and which is electrically connected to the base of the first heterojunction bipolar transistor; a second high electron mobility transistor having a source electrically connected to the reference potential; the third heterojunction bipolar transistor having an emitter electrically connected to a drain of the second high electron mobility transistor, and the base and a collector both electrically connected to the first node; the fourth heterojunction bipolar transistor having a collector electrically connected to a power supply potential, the base electrically connected to the first node, and the emitter electrically connected to the second node; a first resistance electrically connected between the second node and the gate of the first high electron mobility transistor; a second resistance electrically connected between the second node and the gate of the second high electron mobility transistor; and a third resistance electrically connected between the second node and the reference potential. ### Claim 5 (depends on 1) The power amplifier according to claim 1, wherein the second-stage bias circuit comprises: the third node to which a reference current is supplied, and which is electrically connected to the base of the fifth heterojunction bipolar transistor; a fourth high electron mobility transistor having a source electrically connected to the reference potential; the sixth heterojunction bipolar transistor having an emitter electrically connected to a drain of the fourth high electron mobility transistor, and the base and a collector both electrically connected to the third node; the seventh heterojunction bipolar transistor having a collector electrically connected to a power supply potential, the base electrically connected to the third node, and the emitter electrically connected to the fourth node; a fourth resistance electrically connected between the fourth node and the gate of the third high electron mobility transistor; a fifth resistance electrically connected between the fourth node and the gate of the fourth high electron mobility transistor; and a seventh resistance electrically connected between the fourth node and the reference potential. ### Claim 6 (depends on 4) The power amplifier according to claim 4, wherein the initial-stage bias circuit further comprises a resistance electrically connected between the base of the fourth heterojunction bipolar transistor and the first node. ### Claim 7 (depends on 5) The power amplifier according to claim 5, wherein the second-stage bias circuit further comprises a resistance electrically connected between the base of the seventh heterojunction bipolar transistor and the third node. ### Claim 8 (depends on 4) The power amplifier according to claim 4, wherein the initial-stage bias circuit further comprises a resistance electrically connected between the emitter of the fourth heterojunction bipolar transistor and the second node. ### Claim 9 (depends on 5) The power amplifier according to claim 5, wherein the second-stage bias circuit further comprises a resistance electrically connected between the emitter of the seventh heterojunction bipolar transistor and the fourth node. ### Claim 10 (depends on 4) The power amplifier according to claim 4, wherein the initial-stage bias circuit further comprises a resistance electrically connected between the base of the fourth heterojunction bipolar transistor and the first node and a resistance electrically connected between the emitter of the fourth heterojunction bipolar transistor and the second node. ### Claim 11 (depends on 4) The power amplifier according to claim 4, wherein the initial-stage bias circuit further comprises a capacitor electrically connected between the second node and the reference potential. ### Claim 12 (depends on 4) The power amplifier according to claim 4, wherein the initial-stage bias circuit further comprises a capacitor electrically connected between the gate of the second high electron mobility transistor and the reference potential. ### Claim 13 (depends on 4) The power amplifier according to claim 4, wherein the initial-stage bias circuit further comprises a capacitor electrically connected between the gate and the drain of the second high electron mobility transistor. ### Claim 14 (depends on 4) The power amplifier according to claim 4, wherein the initial-stage bias circuit further comprises a capacitor electrically connected between the second node and the drain of the second high electron mobility transistor. ### Claim 15 (depends on 4) The power amplifier according to claim 4, further comprising a reference current generation circuit configured to output the reference current to the first node in accordance with a control signal, wherein the reference current generation circuit comprises: a constant current circuit configured to output the reference current to the first node; a switch configured to selectively electrically connect the first node to the reference potential; and a control circuit configured to control the output of the reference current from the constant current circuit, and to control a state of the switch. ### Claim 16 (depends on 5) The power amplifier according to claim 5, further comprising a reference current generation circuit configured to output the reference current to the third node in accordance with a control signal, wherein the reference current generation circuit comprises: a constant current circuit configured to output the reference current to the third node; a switch configured to selectively electrically connect the third node to the reference potential; and a control circuit configured to control the output of the reference current from the constant current circuit, and to control a state of the switch. ### Claim 17 (depends on 1) A compound semiconductor device comprising the power amplifier according to claim 1, wherein at least the initial-stage amplifier circuit, the second-stage amplifier circuit, the output-stage amplifier circuit, the initial-stage bias circuit, the second-stage bias circuit, and the output-stage bias circuit are formed on a single compound semiconductor chip. ### Claim 18 (depends on 2) A compound semiconductor device comprising the power amplifier according to claim 2, wherein at least the initial-stage amplifier circuit, the second-stage amplifier circuit, the output-stage amplifier circuit, the initial-stage bias circuit, the second-stage bias circuit, and the output-stage bias circuit are formed on a single compound semiconductor chip. ### Claim 19 (depends on 4) A compound semiconductor device comprising the power amplifier according to claim 4, wherein at least the initial-stage amplifier circuit, the second-stage amplifier circuit, the output-stage amplifier circuit, the initial-stage bias circuit, the second-stage bias circuit, and the output-stage bias circuit are formed on a single compound semiconductor chip. ### Claim 20 (depends on 6) A compound semiconductor device comprising the power amplifier according to claim 6, wherein at least the initial-stage amplifier circuit, the second-stage amplifier circuit, the output-stage amplifier circuit, the initial-stage bias circuit, the second-stage bias circuit, and the output-stage bias circuit are formed on a single compound semiconductor chip.