# US 11,309,847 B2 · Amplifier circuit

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- Number: US 11,309,847 B2
- Document ID: US11309847B2
- Status: Granted
- Kind: B2
- Application number: 17/006,020
- Filed: 2020-08-28
- Published: 2021-03-04
- Granted: 2022-04-19
- Earliest claimed: 2019-08-29
- Assignees: Murata Manufacturing Co., Ltd.
- Applicants: Murata Manufacturing Co., Ltd.
- Inventors: Ken Wakaki
- Web page: https://patentgrep.com/patent/US11309847B2

## CPC

- H03F 1/3205: {in field-effect transistor amplifiers}
- H03F 3/16: with field-effect devices
- H03F 3/19: with semiconductor devices only
- H03F 1/0205: {in transistor amplifiers}
- H03F 1/565: {using inductive elements}
- H03F 3/72: Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
- H03F 2200/387: A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
- H03F 2203/7236: the gated amplifier being switched on or off by putting into parallel or not, by choosing between amplifiers by (a ) switch(es)
- H03F 2203/7239: the gated amplifier being switched on or off by putting into parallel or not, by choosing between amplifiers and shunting lines by one or more switch(es)
- H03F: AMPLIFIERS

## Abstract

An amplifier circuit has an amplification path including an amplifier and a bypass path configured to bypass at least the amplifier. The bypass path includes a switch coupled in series on the bypass path and another switch coupled in series between the bypass path and ground. The amplification path further includes an inductor coupled on an output side with respect to the amplifier and a switch coupled between the inductor and ground on a path between the inductor and the amplifier.

## Claims

### Claim 1

An amplifier circuit comprising:
an amplification path that is connected between an input node and an output node, and that comprises an amplifier; and
a bypass path that bypasses at least the amplifier, wherein:
the bypass path comprises:
a first series switch connected in series between the input node and the output node, and
a first shunt switch connected to ground in parallel between the input node and the output node, and
the amplification path further comprises:
an inductor connected to an output side with respect to the amplifier, and
a second shunt switch connected between ground and a first end of the inductor which is opposite to a second end of the inductor at an output node side, wherein the amplifier circuit is configured to operate in:
a bypass mode in which the first series switch is closed, the first shunt switch is open, and the second shunt switch is closed, and
an amplification mode in which the first series switch is open, the first shunt switch is closed, and the second shunt switch is open.

### Claim 2 (depends on 1)

The amplifier circuit according to claim 1, wherein:
the amplification path further comprises a second series switch connected in series between the amplifier and the node between the inductor and the amplifier, and
the second series switch is open in the bypass mode and is closed in the amplification mode.

### Claim 3 (depends on 1)

The amplifier circuit according to claim 1, wherein:
the bypass path further comprises a third series switch connected in series in the bypass path at a position opposite to the first series switch with respect to a connection position of the first shunt switch, and
the third series switch is closed in the bypass mode and open in the amplification mode.

### Claim 4 (depends on 1)

The amplifier circuit according to claim 1, wherein the amplifier comprises a field effect transistor.

### Claim 5 (depends on 1)

The amplifier circuit according to claim 1, wherein the first shunt switch comprises a field effect transistor.

### Claim 6 (depends on 1)

The amplifier circuit according to claim 1, wherein the amplification path further comprises:
a fourth series switch connected in series between the input node and the amplifier, and
a third shunt switch connected between ground and a node between the fourth series switch and the amplifier.

### Claim 7 (depends on 6)

The amplifier circuit according to claim 6, wherein the amplification path further comprises:
a shunt capacitor connected between ground and the node between the fourth series switch and the amplifier, and
a second inductor connected in series between the fourth series switch and the amplifier.

### Claim 8 (depends on 1)

The amplifier circuit according to claim 1, wherein the amplification path further comprises:
a second inductor connected in series between the input node and the amplifier, and
a shunt capacitor connected between ground and a node between the input node and the second inductor.

### Claim 9 (depends on 8)

The amplifier circuit according to claim 8, wherein the amplification path further comprises:
a third shunt switch connected between ground and a node between the second inductor and amplifier.

### Claim 10

An amplifier circuit comprising:
an amplification path that is connected between an input node and an output node, and that comprises an amplifier; and
a bypass path that bypasses at least the amplifier, wherein:
the bypass path comprises:
a first series switch connected in series between the input node and the output node, and
a first shunt switch connected to ground in parallel between the input node and the output node, and
the amplification path further comprises:
an inductor and a second shunt switch connected in series with each other, and in parallel between ground and a node between the amplifier and the output node, wherein the amplifier circuit is configured to operate in:
a bypass mode in which the first series switch is closed, the first shunt switch is open, and the second shunt switch is closed, and
an amplification mode in which the first series switch is open, the first shunt switch is closed, and the second shunt switch is open.

### Claim 11 (depends on 10)

The amplifier circuit according to claim 10, wherein the amplification path further comprises a second series switch connected in series between the amplifier and the node between the amplifier and the output node.

### Claim 12

An amplifier circuit comprising:
an amplification path that is connected between an input node and an output node, and that comprises an amplifier; and
a bypass path that bypasses at least the amplifier, wherein:
the bypass path comprises:
a first series switch connected in series between the input node and the output node, and
a first shunt switch connected to ground in parallel between the input node and the output node, and
the amplification path further comprises:
an inductor connected in series between the amplifier and the output node, and
a second shunt switch connected between ground and a node between the inductor and the amplifier, wherein the amplifier circuit is configured to operate in:
a bypass mode in which the first series switch is closed, the first shunt switch is open, and the second shunt switch is closed, and
an amplification mode in which the first series switch is open, the first shunt switch is closed, and the second shunt switch is open.

### Claim 13 (depends on 12)

The amplifier circuit according to claim 12, wherein the amplification path further comprises a second series switch connected in series between the amplifier and the node between the amplifier and the output node.