# US 11,309,698 B2 · Electrostatic prevention circuit, array substrate and display device

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 11,309,698 B2
- Document ID: US11309698B2
- Status: Granted
- Kind: B2
- Application number: 16/073,987
- Filed: 2017-12-15
- Published: 2021-07-08
- Granted: 2022-04-19
- Earliest claimed: 2017-05-10
- Assignees: Boe Technology Group Co., Ltd.; Beijing Boe Optoelectronics Technology Co., Ltd.
- Applicants: Boe Technology Group Co., Ltd.; Beijing Boe Optoelectronics Technology Co., Ltd.
- Inventors: Haobo Fang; Yanna Xue; Zhiying Bao; Yong Zhang; Lei Mi; Lu Bai; Gang Hua; Jingpeng Wang; Lingxiang Yuan
- Web page: https://patentgrep.com/patent/US11309698B2

## CPC

- H02H 1/063: {primary power being supplied by fault current}
- H10D 89/60: Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
- H02H 9/046: {responsive to excess voltage appearing at terminals of integrated circuits}
- H10D 89/921: {characterised by the configuration of the interconnections connecting the protective arrangements, e.g. ESD buses}
- G02F 1/136204: {Arrangements to prevent high voltage or static electricity failures}
- H10D 89/811: {using FETs as protective elements}
- H10D 89/911: {using passive elements as protective elements}
- H02H: EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS (indicating or signalling undesired working conditions G01R, e.g. G01R31/00, G08B; locating faults along lines G01R31/08; emergency protective devices H01H)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS

## Abstract

An electrostatic prevention circuit, an array substrate and a display device are provided. The electrostatic prevention circuit includes an electrostatic prevention sub-circuit, and the electrostatic prevention sub-circuit includes a thin film transistor and a capacitor; a gate electrode of the thin film transistor is connected to the capacitor, and the thin film transistor is controlled by a signal passing through the capacitor.

## Claims

### Claim 1

An electrostatic prevention circuit, comprising: a first thin film transistor and a first capacitor, wherein,
a gate electrode of the first thin film transistor is connected to a first electrode of the first capacitor;
the electrostatic prevention circuit further comprises a second thin film transistor, a third thin film transistor, a fourth thin film transistor, and a second capacitor;
a second electrode of the first capacitor is connected to a first electrode of the first thin film transistor, a first electrode of the second thin film transistor and a second electrode of the fourth thin film transistor;
a gate electrode of the third thin film transistor is connected to a first electrode of the second capacitor, and a second electrode of the second capacitor is connected to a first electrode of the third thin film transistor, a first electrode of the fourth thin film transistor and a second electrode of the second thin film transistor;
a gate electrode of the second thin film transistor is connected to a second electrode of the first thin film transistor; and
a gate electrode of the fourth thin film transistor is connected to a second electrode of the third thin film transistor.

### Claim 2 (depends on 1)

The electrostatic prevention circuit according to claim 1, wherein, the first thin film transistor, the second thin film transistor, the third thin film transistor and the fourth thin film transistor are an N-type MOS thin film transistor.

### Claim 3 (depends on 1)

An array substrate, comprising the electrostatic prevention circuit according to claim 1.

### Claim 4 (depends on 3)

The array substrate according to claim 3, further comprising a first connection structure and a second connection structure, wherein,
a first terminal of the electrostatic prevention circuit and a second terminal of the electrostatic prevention circuit are connected to the first connection structure and the second structure respectively.

### Claim 5 (depends on 4)

The array substrate according to claim 4, wherein, each of the first connection structure and the second connection structure is a signal line or a short-circuit ring.

### Claim 6 (depends on 5)

The array substrate according to claim 5, wherein, the signal line is a gate signal line and or a data signal line, and the short-circuit ring is a gate signal line short-circuit ring or a data signal line short-circuit ring.

### Claim 7 (depends on 3)

The array substrate according to claim 3, wherein,
the array substrate comprises a plurality of the electrostatic prevention circuits and a plurality of connection structures, a first terminal of each of the electrostatic prevention circuits is connected to a same one of the connection structures, and a second terminal of each of the electrostatic prevention circuits is connected to different ones of the connection structures.

### Claim 8 (depends on 7)

The array substrate according to claim 7, wherein, each of the connection structures is a signal line or a short-circuit ring.

### Claim 9 (depends on 8)

The array substrate according to claim 8, wherein, the signal line is a gate signal line or a data signal line, and the short-circuit ring is a gate signal line short-circuit ring or a data signal line short-circuit ring.

### Claim 10 (depends on 3)

The array substrate according to claim 3, wherein,
the array substrate comprises a plurality of the electrostatic prevention circuits, a first connection structure and a second connection structure, a first terminal of each of the electrostatic prevention circuits is connected to the first connection structure, and a second terminal of each of the electrostatic prevention circuits is connected to the second connection structure.

### Claim 11 (depends on 3)

A display device, comprising the array substrate according to claim 3.