# US 11,309,503 B2 · Transistor manufacturing method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,309,503 B2 - Document ID: US11309503B2 - Status: Granted - Kind: B2 - Application number: 16/374,805 - Filed: 2019-04-04 - Published: 2019-07-25 - Granted: 2022-04-19 - Earliest claimed: 2013-11-21 - Assignees: Nikon Corporation - Applicants: Nikon Corporation - Inventors: Shohei Koizumi; Takashi Sugizaki; Yusuke Kawakami - Web page: https://patentgrep.com/patent/US11309503B2 ## CPC - H10K 10/464: {Lateral top-gate IGFETs comprising only a single gate} - C23C 18/1605: {by masking} - C23C 18/31: Coating with metals - C23C 18/32: Coating with nickel, cobalt or mixtures thereof with phosphorus or boron (C23C18/50 takes precedence) - C23C 28/00: Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D - G03F 7/20: Exposure; Apparatus therefor (photographic printing apparatus for making copies G03B27/00) - G03F 7/32: Liquid compositions therefor, e.g. developers - G03F 7/40: Treatment after imagewise removal, e.g. baking - H10D 30/67: Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)} - H10D 30/6737: {characterised by the electrode materials} - H10D 30/6739: {Conductor-insulator-semiconductor electrodes} - H10D 30/6743: {Silicon} - H10D 64/62: Electrodes ohmically coupled to a semiconductor - H10D 86/441: {Interconnections, e.g. scanning lines} - H10D 86/60: wherein the TFTs are in active matrices - H10K 10/466: {Lateral bottom-gate IGFETs comprising only a single gate} - H10K 71/621: {Providing a shape to conductive layers, e.g. patterning or selective deposition} - C23C 18/1651: {Two or more layers only obtained by electroless plating} - C23C 18/30: Activating {or accelerating or sensitising with palladium or other noble metal} - C23C 18/34: using reducing agents - C23C 18/42: Coating with noble metals - H10K 71/135: {using ink-jet printing} - H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES - C23C: COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL (making metal-coated products by extrusion B21C23/22; covering with metal by connecting pre-existing layers to articles, see the relevant places, e.g. B21D39/00, B23K; metallising of glass C03C; metallising mortars, concrete, artificial stone, ceramics or natural stone C04B41/00; enamelling of, or applying a vitreous layer to, metals C23D; treating metal surfaces or coating of metals by electrolysis or electrophoresis C25D; single-crystal film growth C30B; by metallising textiles D06M11/83; decorating textiles by locally metallising D06Q1/04) - G03F: PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR; (phototypographic composing devices B41B; photosensitive materials or processes for photographic purposes G03C; electrophotography, sensitive layers or processes therefor G03G) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A transistor manufacturing method includes forming a source electrode and a drain electrode on a substrate, forming a layer including an insulator layer to cover the source electrode and the drain electrode, and forming a gate electrode on the layer including the insulator layer, wherein the forming the gate electrode includes forming a plating base film, forming a protection layer of the plating base film, forming a photoresist layer on the protection layer to expose the photoresist layer with desired patterning light, causing the exposed photoresist layer to come into contact with a developer to remove the photoresist layer and the protection layer until the plating base film is uncovered corresponding to the patterning light, and after depositing a metal on the uncovered plating base film, causing an electroless plating solution to come into contact with the plating base film to perform electroless plating. ## Claims ### Claim 1 A transistor manufacturing method comprising: forming a source electrode and a drain electrode on a substrate; forming a layer including an insulator layer to cover the source electrode and the drain electrode; and forming a gate electrode, wherein the forming the gate electrode comprises applying a liquid body including a first formation material on at least part of the layer including the insulator layer to form a plating base film; applying a liquid body including a second formation material on at least part of a surface of the plating base film to form a protection layer of the plating base film; forming a photoresist layer that includes a photoresist material on a surface of the protection layer to expose the photoresist layer with desired patterning light; causing the exposed photoresist layer to come into contact with a developer to remove the photoresist layer and the protection layer until the plating base film is uncovered corresponding to the patterning light; and after depositing a metal as a catalyst for electroless plating on a surface of the uncovered plating base film, causing an electroless plating solution to come into contact with the catalyst on the surface of the plating base film to perform electroless plating, and wherein the transistor manufacturing method comprises exfoliating the protection layer and the photoresist layer after performing the electroless plating. ### Claim 2 (depends on 1) The transistor manufacturing method according to claim 1, wherein the second formation material is an organic silicon compound having a hydrolysis group that is bonded to a silicon atom. ### Claim 3 (depends on 2) The transistor manufacturing method according to claim 2, wherein the second formation material is an organic silicon compound having one hydrolysis group that is bonded to the silicon atom. ### Claim 4 (depends on 2) The transistor manufacturing method according to claim 2, wherein the second formation material is an organic silicon compound having two or three hydrolysis groups that are bonded to the silicon atom. ### Claim 5 (depends on 1) The transistor manufacturing method according to claim 1, wherein the first formation material is a silane coupling agent that includes a group having at least one of a nitrogen atom and a sulfur atom. ### Claim 6 (depends on 5) The transistor manufacturing method according to claim 5, wherein the silane coupling agent has an amino group. ### Claim 7 (depends on 6) The transistor manufacturing method according to claim 6, wherein the silane coupling agent is a primary amine or a secondary amine. ### Claim 8 (depends on 1) The transistor manufacturing method according to claim 1, wherein the substrate is made of a non-metallic material. ### Claim 9 (depends on 8) The transistor manufacturing method according to claim 8, wherein the substrate is made of a resin material. ### Claim 10 (depends on 9) The transistor manufacturing method according to claim 9, wherein the substrate has flexibility. ### Claim 11 (depends on 9) The transistor manufacturing method according to claim 9, wherein the plating base film is formed by a heat treatment at a heating temperature that is lower than a deformation temperature of the substrate. ### Claim 12 A transistor manufacturing method comprising: forming a source electrode and a drain electrode on a substrate; forming a layer including an insulator layer to cover the source electrode and the drain electrode; and forming a gate electrode, wherein the forming the source electrode and the drain electrode on the substrate includes forming at least one of the source electrode and the drain electrode by: applying a liquid body including a first formation material on at least part of the substrate to form a plating base film; applying a liquid body including a second formation material on at least part of a surface of the plating base film to form a protection layer of the plating base film; forming a photoresist layer that includes a photoresist material on an upper surface of the protection layer to expose the photoresist layer with desired patterning light; causing the exposed photoresist layer to come into contact with a developer to remove the photoresist layer and the protection layer until the plating base film is uncovered corresponding to the patterning light; and after depositing a metal as a catalyst for electroless plating on a surface of the uncovered plating base film, causing an electroless plating solution to come into contact with the catalyst on the surface of the plating base film to perform electroless plating, and wherein the transistor manufacturing method comprises exfoliating the protection layer and the photoresist layer after performing the electroless plating.