# US 11,309,491 B2 · Data storage structure for improving memory cell reliability

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- Number: US 11,309,491 B2
- Document ID: US11309491B2
- Status: Granted
- Kind: B2
- Application number: 16/788,611
- Filed: 2020-02-12
- Published: 2021-03-04
- Granted: 2022-04-19
- Earliest claimed: 2019-08-26
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Hai-Dang Trinh; Chii-Ming Wu; Cheng-Yuan Tsai; Tzu-Chung Tsai; Fa-Shen Jiang
- Web page: https://patentgrep.com/patent/US11309491B2

## CPC

- H10N 70/24: {based on migration or redistribution of ionic species, e.g. anions, vacancies}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/021: {Formation of switching materials, e.g. deposition of layers}
- H10N 70/063: {by etching of pre-deposited switching material layers, e.g. lithography}
- H10N 70/883: {Oxides or nitrides}
- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- H10N 70/8836: {Complex metal oxides, e.g. perovskites, spinels}
- G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites}
- G11C 13/003: {Cell access}
- G11C 2213/50: Resistive cell structure aspects
- G11C 2213/71: Three dimensional array
- G11C 2213/79: Array wherein the access device being a transistor
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays}
- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Various embodiments of the present disclosure are directed towards a memory cell including a data storage structure. A top electrode overlies a bottom electrode. The data storage structure is disposed between the top electrode and the bottom electrode. The data storage structure includes a first data storage layer, a second data storage layer, and a third data storage layer. The second data storage layer is disposed between the first and third data storage layers. The second data storage layer has a lower bandgap than the third data storage layer. The first data storage layer has a lower bandgap than the second data storage layer.

## Claims

### Claim 1

A memory cell comprising:
a bottom electrode;
a top electrode overlying the bottom electrode; and
a data storage structure disposed between the top and bottom electrodes, wherein the data storage structure comprises a first data storage layer, a second data storage layer, and a third data storage layer, wherein the second data storage layer is disposed between the first and third data storage layers, wherein the second data storage layer has a lower bandgap than the third data storage layer, and wherein the first data storage layer has a lower bandgap than the second data storage layer.

### Claim 2 (depends on 1)

The memory cell of claim 1, wherein the first data storage layer comprises a different material than the second and third data storage layers.

### Claim 3 (depends on 1)

The memory cell of claim 1, wherein a conductive path is formable and dissolvable within a region of the data storage structure to couple the bottom electrode to the top electrode.

### Claim 4 (depends on 1)

The memory cell of claim 1, wherein a thickness of the first data storage layer is less than a thickness of the second data storage layer, and wherein the thickness of the second data storage layer is less than a thickness of the third data storage layer.

### Claim 5 (depends on 1)

The memory cell of claim 1, wherein a width of the first data storage layer discretely increases in a direction towards the bottom electrode.

### Claim 6 (depends on 1)

The memory cell of claim 1, wherein the first data storage layer comprises metal atoms and oxygen atoms, wherein a bond between the metal atoms and oxygen atoms is greater than 600 kilojoules per mole.

### Claim 7 (depends on 1)

The memory cell of claim 1, further comprising:
a sidewall spacer structure laterally surrounding sidewalls of the top electrode and the data storage structure, wherein a bottom surface of the sidewall spacer structure directly contacts an upper surface of the first data storage layer.

### Claim 8 (depends on 1)

The memory cell of claim 1, wherein a minimum width of the bottom electrode is greater than a maximum width of the top electrode.

### Claim 9 (depends on 1)

The memory cell of claim 1, wherein the first data storage layer comprises a first pair of opposing sidewalls and a second pair of opposing sidewalls, wherein the first pair of opposing sidewalls are spaced laterally between the second pair of opposing sidewalls.

### Claim 10

A memory device comprising:
a bottom electrode;
a top electrode overlying the bottom electrode; and
a data storage structure disposed between the bottom electrode and the top electrode, wherein the data storage structure comprises:
a first data storage layer contacting the bottom electrode and comprising a first material;
a second data storage layer contacting the first data storage layer and comprising a second material different from the first material;
a third data storage layer disposed between the second data storage layer and the top electrode, wherein the third data storage layer comprises a third material different from the first material and the second material, wherein the first, second, and third materials respectively comprise a metal oxide; and
wherein respective bandgaps of the first, second, and third data storage layers gradually decrease or increase from the top electrode to the bottom electrode, wherein the top electrode is configured to receive a programming voltage and the bottom electrode is configured to receive a reference voltage.

### Claim 11 (depends on 10)

The memory device of claim 10, wherein outer sidewalls of the third data storage layer are aligned with outer sidewalls of the top electrode.

### Claim 12 (depends on 10)

The memory device of claim 10, wherein sidewalls of the third data storage layer are aligned with sidewalls of the bottom electrode.

### Claim 13 (depends on 10)

The memory device of claim 10, wherein a first bandgap of the first data storage layer is less than 4.5 eV.

### Claim 14 (depends on 10)

The memory device of claim 10, further comprising:
a capping layer overlying the top electrode;
a top electrode via overlying the capping layer; and
a sidewall spacer structure continuously extending from sidewalls of the data storage structure to a sidewall of the top electrode via, wherein the sidewall spacer structure contacts an upper surface of the capping layer.

### Claim 15 (depends on 10)

The memory device of claim 10, wherein the first data storage layer comprises a pair of vertical opposing sidewalls and a pair of slanted opposing sidewalls, wherein the pair of vertical opposing sidewalls overlie the pair of slanted opposing sidewalls.

### Claim 16 (depends on 10)

The memory device of claim 10, wherein a maximum width of the first data storage layer is greater than a maximum width of the third data storage layer.

### Claim 17

A memory device comprising:
a substrate; and
a resistive random access memory (RRAM) cell overlying the substrate, wherein the RRAM cell comprises a top electrode, a bottom electrode, and a data storage structure disposed between the top electrode and the bottom electrode, wherein a bandgap of the data storage structure discretely decreases at least two times from a top surface of the data storage structure in a direction towards the substrate.

### Claim 18 (depends on 17)

The memory device of claim 17, wherein the data storage structure comprises a top data storage layer, a bottom data storage layer, and a middle data storage layer disposed between the top data storage layer and the bottom data storage layer.

### Claim 19 (depends on 18)

The memory device of claim 18, wherein a thickness of the top data storage layer is greater than a thickness of the middle data storage layer, and wherein the thickness of the middle data storage layer is greater than a thickness of the bottom data storage layer.

### Claim 20 (depends on 18)

The memory device of claim 18, wherein the top data storage layer, the bottom data storage layer, and the middle data storage layer respectively comprises different high-k dielectric materials from one another.