# US 11,309,478 B2 · Enhanced superconducting transition temperature in electroplated Rhenium

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- Number: US 11,309,478 B2
- Document ID: US11309478B2
- Status: Granted
- Kind: B2
- Application number: 17/221,346
- Filed: 2021-04-02
- Published: 2021-07-22
- Granted: 2022-04-19
- Earliest claimed: 2018-02-28
- Assignees: The Regents of the University of Colorado, a body corporate; The Government of the United States of America, as represented by the Secretary of Commerce National Institite of Standards and Technology
- Applicants: The Regents of the University of Colorado, a body corporate
- Inventors: Donald David; David Pappas; Xian Wu
- Web page: https://patentgrep.com/patent/US11309478B2

## CPC

- H05K 3/241: {characterised by the electroplating method; means therefor, e.g. baths or apparatus}
- H10N 60/85: Superconducting active materials
- B32B 15/043: {of metal (B32B15/01 takes precedence)}
- H01B 12/02: characterised by their form
- H10N 60/01: Manufacture or treatment
- H10N 60/20: Permanent superconducting devices
- B32B 2255/06: on metal layer
- B32B 2255/205: Metallic coating
- B32B 2307/202: Conductive
- B32B 2457/08: PCBs, i.e. printed circuit boards
- H01B 12/06: Films or wires on bases or cores
- H05K 3/181: {by electroless plating (adhesives therefor H05K3/387)}
- H05K 2201/0338: Layered conductor, e.g. layered metal substrate, layered finish layer or layered thin film adhesion layer
- H05K 2201/0391: Using different types of conductors
- H05K 2203/0723: Electroplating, e.g. finish plating
- H05K 2203/1476: Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- B32B: LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- H01B: CABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES (selection for magnetic properties H01F1/00; waveguides H01P {; printed circuits H05K})

## Abstract

This disclosure describes systems, methods, and apparatus for multilayer superconducting structures comprising electroplated Rhenium, where the Rhenium operates in a superconducting regime at or above 4.2 K, or above 1.8 K where specific temperatures and times of annealing have occurred. The structure can include at least a first conductive layer applied to a substrate, where the Rhenium layer is electroplated to the first layer. A third layer formed from the same or a different conductor as the first layer can be formed atop the Rhenium layer.

## Claims

### Claim 1

A superconducting circuit system comprising:
a means for maintaining the circuit at or below 6.0 K;
a substrate having a circular cross section;
a first conductive layer bonded to the substrate;
an amorphous Re layer deposited over the first conductive layer using electroplating, and the amorphous Re layer having a thickness of between 10 nm and 1000 nm; and
a second conductive layer bonded to the amorphous Re layer.

### Claim 2 (depends on 1)

The superconducting circuit system of claim 1, wherein the first and second conductive layers are immiscible with the amorphous Re layer.

### Claim 3 (depends on 1)

The superconducting circuit system of claim 1, wherein the second conductive layer encapsulates the amorphous Re layer.

### Claim 4 (depends on 1)

The superconducting circuit system of claim 1, wherein the means for maintaining the circuit at or below 6.0 K is a means for maintaining the circuit at or below 5.0 K.

### Claim 5 (depends on 1)

The superconducting circuit system of claim 1, further comprising one or more additional pairs of layers between the first conductive layer and the amorphous Re layer and wherein each of the one or more additional pairs of layers comprise another amorphous Re layer and another conductive layer.

### Claim 6 (depends on 1)

The superconducting circuit system of claim 1, wherein either or both of the first and second conductive layers are independently chosen from the group comprising Cu, Au, Pt, Pd, Ni, Rh, Ru, and Sn.

### Claim 7 (depends on 1)

The superconducting circuit system of claim 1, wherein the first conductive layer is less than 100 nm in thickness, and wherein the first conductive layer in isolation is non-superconducting or a low-Tc superconductor, but when bonded to the amorphous Re layer becomes a high-Tc superconductor via proximitization.

### Claim 8

A superconducting circuit system comprising:
a means for maintaining the circuit at or below 6.0 K;
a substrate;
a first conductive layer bonded to the substrate;
an amorphous Re layer deposited over the first conductive layer using electroplating, and the amorphous Re layer having a thickness of between 10 nm and 1000 nm;
a second conductive layer bonded to the amorphous Re layer; and
one or more additional pairs of layers between the first conductive layer and the amorphous Re layer and wherein each of the one or more additional pairs of layers comprise another amorphous Re layer and another conductive layer.

### Claim 9 (depends on 8)

The superconducting circuit system of claim 8, wherein the first and second conductive layers are immiscible with the amorphous Re layer.

### Claim 10 (depends on 8)

The superconducting circuit system of claim 8, wherein the second conductive layer encapsulates the amorphous Re layer.

### Claim 11 (depends on 1)

The superconducting circuit system of claim 1, wherein the means for maintaining the circuit at or below 6.0 K is a means for maintaining the circuit at or below 5.0 K.

### Claim 12 (depends on 8)

The superconducting circuit system of claim 8, wherein the substrate has a circular cross section.

### Claim 13 (depends on 8)

The superconducting circuit system of claim 8, wherein either or both of the first and second conductive layers are independently chosen from the group comprising Cu, Au, Pt, Pd, Ni, Rh, Ru, and Sn.

### Claim 14 (depends on 8)

The superconducting circuit system of claim 8, wherein the first conductive layer is less than 100 nm in thickness, and wherein the first conductive layer in isolation is non-superconducting or a low-Tc superconductor, but when bonded to the amorphous Re layer becomes a high-Tc superconductor via proximitization.

### Claim 15

A method of fabricating at least one superconducting circuit on a multilayer circuit board, the method comprising:
forming a via between at least two layers of the multilayer circuit board;
applying a first conductive layer onto a wall of the via by electroless plating;
electroplating an amorphous Re layer above the first conductive layer to a thickness of between 10 nm to 1000 nm;
applying a second conductive layer onto the amorphous Re layer; wherein
the superconducting circuit is superconducting at or above 4.2K.

### Claim 16 (depends on 15)

The method of claim 15, wherein the first conductive layer is immiscible with the amorphous Re layer.

### Claim 17 (depends on 15)

The method of claim 15, wherein the second conductive layer encapsulates the amorphous Re layer.

### Claim 18 (depends on 15)

The method of claim 15, further comprising making a wire bond or solder connection between the second conductive layer and another circuit or between the first conductive layer and an internal conductive trace of the multilayer circuit board.

### Claim 19 (depends on 15)

The method of claim 15, further comprising, after applying the second conductive layer onto the amorphous Re layer, annealing the superconducting circuit at 100-150° C. for up to 10 minutes.

### Claim 20 (depends on 15)

The method of claim 15, further comprising making the first conductive layer a high-Tc superconductor via proximity effect and bonding with the amorphous Re layer.