# US 11,309,435 B2 · Bandgap reference circuit including vertically stacked active SOI devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,309,435 B2 - Document ID: US11309435B2 - Status: Granted - Kind: B2 - Application number: 16/812,583 - Filed: 2020-03-09 - Published: 2021-09-09 - Granted: 2022-04-19 - Earliest claimed: 2020-03-09 - Assignees: GlobalFoundries U.S. Inc. - Applicants: GLOBALFOUNDRIES U.S. Inc. - Inventors: Don Raymond Blackwell; Peter P. Hang; Van Ton-That; Timothy S. Miller - Web page: https://patentgrep.com/patent/US11309435B2 ## CPC - G05F 3/30: Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities (G05F3/26 takes precedence) - H10D 30/831: {Vertical FETs having PN junction gate electrodes (Vertical SIT H10D30/202)} - H10D 1/025: {of resistors having potential barriers} - H10D 8/411: {PN diodes having planar bodies} - H10D 62/103: {for increasing or controlling the breakdown voltage of reverse-biased devices} - H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions - H10D 87/00: Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate - H10P 14/3442: {N-type} - H10P 14/3444: {P-type} - H10W 10/031: {of isolation regions comprising PN junctions} - H10W 10/30: Isolation regions comprising PN junctions - H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors} - H10D 88/00: Three-dimensional [3D] integrated devices - H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations} - H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations - G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Embodiments of the disclosure provide a bandgap reference circuit, including: first and second vertically stacked structures, the first and second vertically stacked structures each including: a P-type substrate; a P-well region within the P-type substrate; an N-type barrier region between the P-type substrate and the P-well region, the P-well region and the N-type barrier region forming a PN junction; a field effect transistor (FET) above the P-well region, separated from the P-well region by a buried insulator layer, the P-well region forming a back gate of the FET; and a first voltage source coupled to the P-well and applying a forward bias to a diode formed at the PN junction between the P-well region and the N-type barrier region. ## Claims ### Claim 1 A bandgap reference circuit, comprising: first and second vertically stacked structures, the first and second vertically stacked structures each including: a P-type substrate; a P-well region within the P-type substrate; an N-type barrier region between the P-type substrate and the P-well region, the P-well region and the N-type barrier region forming a PN junction; a field effect transistor (FET) above the P-well region, separated from the P-well region by a buried insulator layer, the P-well region forming a back gate of the FET; and a first voltage source coupled to the P-well and applying a forward bias to a diode formed at the PN junction between the P-well region and the N-type barrier region. ### Claim 2 (depends on 1) The bandgap reference circuit according to claim 1, wherein first voltage source concurrently biases the back gate of the FET. ### Claim 3 (depends on 1) The bandgap reference circuit according to claim 1, further comprising: a second voltage source coupled to the N-type barrier region and applying a reverse bias to a PN junction formed between the P-type substrate and the N-type barrier region; and a third voltage source coupled to the P-type substrate and applying a reverse bias to the PN junction formed between the P-type substrate and the N-type barrier region. ### Claim 4 (depends on 1) The bandgap reference circuit according to claim 1, wherein the N-type barrier region and the P-type substrate are connected to ground. ### Claim 5 (depends on 1) The bandgap reference circuit according to claim 1, wherein the FET in the first vertically stacked structure and the FET in the second vertically stacked structure form a current mirror. ### Claim 6 (depends on 1) The bandgap reference circuit according to claim 1, wherein the FET in each of the first and second vertically stacked structures includes a source, a drain, and a gate, and wherein the bandgap reference circuit further comprises an operational amplifier, the operational amplifier having an output coupled to the gate of the FET in each of the first and second vertically stacked structures. ### Claim 7 (depends on 6) The bandgap reference circuit according to claim 6, wherein the operational amplifier includes a first input coupled to a first node and a second input coupled to a second node, wherein the first node is coupled to a back gate of the FET in the first vertically stacked structure. ### Claim 8 (depends on 7) The bandgap reference circuit according to claim 7, wherein the bandgap reference circuit further comprises: a first resistor coupled between the second node and the back gate of the FET in the second vertically stacked structure; a second resistor coupled between the second node and the drain of the FET in the second vertically stacked structure; and a third resistor coupled between the first node and a drain of the FET in the first vertically stacked structure. ### Claim 9 (depends on 8) The bandgap reference circuit according to claim 8, wherein a voltage across the first resistor is a proportional to absolute temperature (PTAT) voltage, and wherein a voltage across the diode formed at the PN junction between the P-well region and the N-type barrier region in each of the first and second stacked devices is a complementary to absolute temperature (CTAT) voltage. ### Claim 10 (depends on 9) The bandgap reference circuit according to claim 9, further comprising an output node connected to the second and third resistors, the output node outputting a reference voltage. ### Claim 11 (depends on 6) The bandgap reference circuit according to claim 6, wherein the source of the FET in each of the first and second vertically stacked structures is coupled to a supply voltage. ### Claim 12 An integrated circuit, comprising: a bandgap reference circuit for generating a reference current, the bandgap reference circuit comprising: first and second vertically stacked structures, the first and second vertically stacked structures each including: a P-type substrate; a P-well region within the P-type substrate; an N-type barrier region between the P-type substrate and the P-well region, the P-well region and the N-type barrier region forming a PN junction; a field effect transistor (FET) above the P-well region, separated from the P-well region by a buried insulator layer, the P-well region forming a back gate of the FET, wherein the FET in the first vertically stacked structure and the FET in the second vertically stacked structure form a current mirror; and a first voltage source coupled to the P-well and applying a forward bias to a diode formed at the PN junction between the P-well region and the N-type barrier region, wherein the first voltage source concurrently biases the back gate of the FET. ### Claim 13 (depends on 12) The integrated circuit according to claim 12, further comprising: a second voltage source coupled to the N-type barrier region and applying a reverse bias to a PN junction formed between the P-type substrate and the N-type barrier region; and a third voltage source coupled to the P-type substrate and applying a reverse bias to the PN junction formed between the P-type substrate and the N-type barrier region. ### Claim 14 (depends on 12) The integrated circuit according to claim 12, wherein the FET in each of the first and second vertically stacked structures includes a source, a drain, and a gate, and wherein the bandgap reference circuit further comprises an operational amplifier, the operational amplifier including: an output coupled to the gate of the FET in each of the first and second vertically stacked structures; and a first input coupled to a first node and a second input coupled to a second node, wherein the first node is coupled to a back gate of the FET in the first vertically stacked structure; wherein the bandgap reference circuit further comprises: a first resistor coupled between the second node and the back gate of the FET in the second vertically stacked structure; a second resistor coupled between the second node and the drain of the FET in the second vertically stacked structure; and a third resistor coupled between the first node and a drain of the FET in the first vertically stacked structure. ### Claim 15 (depends on 14) The integrated circuit according to claim 14, wherein a voltage across the first resistor is a proportional to absolute temperature (PTAT) voltage, and wherein a voltage across the diode formed at the PN junction between the P-well region and the N-type barrier region in each of the first and second stacked devices is a complementary to absolute temperature (CTAT) voltage. ### Claim 16 (depends on 14) The integrated circuit according to claim 14, further comprising an output node connected to the second and third resistors, the output node outputting a reference voltage. ### Claim 17 A bandgap reference circuit with vertically stacked active silicon-on-insulator (SOI) devices, comprising: a P-type substrate; a P-well region within the P-type substrate; an N-type barrier region between the P-type substrate and the P-well region, the P-well region and the N-type barrier region forming a PN junction; a field effect transistor (FET) above the P-well region, separated from the P-well region by a buried insulator layer, the P-well region forming a back gate of the FET; and a first voltage source coupled to the P-well and applying a forward bias to a diode formed at the PN junction between the P-well region and the N-type barrier region, wherein the first voltage source concurrently biases the back gate of the FET. ### Claim 18 (depends on 17) The bandgap reference circuit according to claim 17, wherein the N-type barrier region and the P-type substrate are connected to ground. ### Claim 19 (depends on 17) The bandgap reference circuit according to claim 17, further comprising a resistor coupled to the back gate of the FET, wherein a voltage across the resistor is a proportional to absolute temperature (PTAT) voltage, and wherein a voltage across the diode formed at the PN junction between the P-well region and the N-type barrier region is a complementary to absolute temperature (CTAT) voltage.