# US 11,309,432 B2 · Nanometer semiconductor devices having high-quality epitaxial layer

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 11,309,432 B2
- Document ID: US11309432B2
- Status: Granted
- Kind: B2
- Application number: 16/586,703
- Filed: 2019-09-27
- Published: 2020-01-23
- Granted: 2022-04-19
- Earliest claimed: 2015-12-07
- Assignees: Institute of Microelectronics, Chinese Academy of Sciences
- Applicants: Institute of Microelectronics, Chinese Academy of Sciences
- Inventors: Huilong Zhu
- Web page: https://patentgrep.com/patent/US11309432B2

## CPC

- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/502: {characterised by the stacked channels}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6741: {Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755)}
- H10D 30/6743: {Silicon}
- H10D 30/675: {Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/364: {of IGFETs}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

There are provided a nanometer semiconductor device with a high-quality epitaxial layer and a method of manufacturing the same. According to an embodiment, the semiconductor device may include: a substrate; at least one nanowire spaced apart from the substrate; at least one semiconductor layer, each formed around a periphery of respective one of the at least one nanowire to at least partially surround the corresponding nanowire, wherein the semiconductor layer(s) formed around the respective nanowire(s) are separated from each other; an isolation layer formed on the substrate, exposing the at least one semiconductor layer; and a gate stack formed on the isolation layer and intersecting the at least one semiconductor layer, wherein the gate stack includes a gate dielectric layer at least partially surrounding a periphery of respective one of the at least one semiconductor layer and a gate conductor layer.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, comprising:
forming a fin structure on a substrate;
forming a supporting layer on the substrate having the fin structure formed thereon, and patterning the supporting layer into a supporting portion extending from a surface of the substrate to a surface of the fin structure and thereby physically connecting the fin structure to the substrate;
removing a portion of the tin structure, to form at least one nanowire spaced apart from the substrate;
growing semiconductor layers with respective one of the at least one nanowire as a seed layer;
depositing a dielectric material and then etching the dielectric material back to expose the respective semiconductor layers, thus forming an isolation layer that isolates a semiconductor layer of the semiconductor layers closest to the substrate; and
forming a gate stack intersecting the semiconductor layers on the isolation layer, wherein forming a gate stack comprises: forming a gate dielectric layer at least partially surrounding a periphery of respective one of the semiconductor layers; and forming a gate conductor layer on the isolation layer.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the fin structure comprises a stack of sacrificial layer(s) and nanowire material layer(s) alternately stacked on the substrate.

### Claim 3 (depends on 2)

The method according to claim 2, wherein forming a fin structure comprises: patterning the nanowire material layer(s) and the sacrificial layer(s) sequentially into a fin structure.

### Claim 4 (depends on 2)

The method according to claim 2, wherein removing a portion of the fin structure comprises: selectively removing the sacrificial layer(s).

### Claim 5 (depends on 1)

The method according to claim 1, wherein the semiconductor layer is grown by a selective growth method.

### Claim 6 (depends on 1)

The method according to claim 1, wherein when forming the isolation layer, a portion of the isolation layer between the semiconductor layer closest to the substrate and the substrate and another portion of the isolation layer between the respective semiconductor layers remain to serve as a mask layer.

### Claim 7 (depends on 1)

The method according to claim 1, wherein patterning into a supporting portion comprises:
forming a mask to shield a portion of the supporting layer, wherein the mask extends on the fin structure beyond an extent of the fin structure in a direction perpendicular to a longitudinal direction of the fin structure, and the mask covers only a fraction of a length of the fin structure in the longitudinal direction;
selectively removing a portion of the supporting layer which is not shielded; and
removing the mask.

### Claim 8 (depends on 7)

The method according to claim 7, wherein forming a mask comprises:
covering either one or both of opposite ends of the fin structure with the mask or covering the middle of the fin structure with the mask.

### Claim 9 (depends on 7)

The method according to claim 7, wherein forming a supporting layer comprises:
depositing an oxide layer and a nitride layer in sequence in a substantially conformal manner.

### Claim 10 (depends on 9)

The method according to claim 9, wherein the oxide layer has a thickness of about 1-10 nm and the nitride layer has a thickness of about 2-15 nm.

### Claim 11 (depends on 1)

The method according to claim 1, wherein the at least one nanowire comprises Si, and the at least one semiconductor layer comprises Ge, SiGe, or a MN compound semiconductor.

### Claim 12

A method of manufacturing a semiconductor device, comprising:
forming a fin structure on a substrate;
forming a supporting layer on the substrate having the fin structure formed thereon, and patterning the supporting layer into a supporting portion extending from a surface of the substrate to a surface of the fin structure and thereby physically connecting the fin structure to the substrate;
removing a portion of the tin structure, to form at least one nanowire spaced apart from the substrate;
growing semiconductor layers with respective one of the at least two nanowire as a seed layer;
depositing a dielectric material and then etching the dielectric material back to expose the respective semiconductor layers, thus forming an isolation layer that isolates a semiconductor layer of the semiconductor layers closest to the substrate;
forming a mask layer between the substrate and one of the semiconductor lavers closest the substrate as well as between the respective semiconductor layers;
selectively etching the respective semiconductor layers with the at least one nanowire and the mask layer as a mask, so that portions of the semiconductor layers between the respective nanowire(s) and the mask layer remain;
selectively removing the nanowire(s) and the mask layer; and
forming a gate stack intersecting the semiconductor layers on the isolation laver, wherein forming a gate stack comprises: forming a gate dielectric layer at least partially surrounding a periphery of respective one of the semiconductor layers; and forming a gate conductor layer on the isolation layer.