# US 11,309,431 B2 · Memory device, semiconductor device, and electronic device

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- Number: US 11,309,431 B2
- Document ID: US11309431B2
- Status: Granted
- Kind: B2
- Application number: 17/053,467
- Filed: 2019-05-07
- Published: 2021-08-26
- Granted: 2022-04-19
- Earliest claimed: 2018-05-17
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Takahiko Ishizu; Kazuma Furutani
- Web page: https://patentgrep.com/patent/US11309431B2

## CPC

- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- G11C 11/405: with three charge-transfer gates, e.g. MOS transistors, per cell
- G11C 11/4091: Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
- G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers
- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- G11C 11/4097: Bit-line organisation, e.g. bit-line layout, folded bit lines
- H10B 12/00: Dynamic random access memory [DRAM] devices
- H10B 12/50: {Peripheral circuit region structures}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 88/01: {Manufacture or treatment}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A memory device which includes a gain-cell memory cell formed using an n-channel transistor and in which a potential lower than a potential applied to a bit line is not necessary is provided. Memory cells included in the memory device are arranged in a matrix, and each of the memory cells is connected to a write word line, a write bit line, a read word line, and a read bit line. The write word line is arranged in parallel to one of directions of a row and a column of memory cells arranged in a matrix, and the write bit line is arranged in parallel to the other of the directions of the row and the column. The read word line is arranged in parallel to the one of the directions of the row and the column of the memory cells arranged in a matrix, and the read bit line is arranged in parallel to the other of the directions of the row and the column.

## Claims

### Claim 1

A semiconductor device comprising:
first to fifth wirings; and
first and second transistors,
wherein the second transistor comprises a front gate and a back gate,
wherein one of a source and a drain of the first transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to a front gate of the second transistor,
wherein a gate of the first transistor is electrically connected to the third wiring,
wherein one of a source and a drain of the second transistor is electrically connected to the second wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to the fourth wiring,
wherein the back gate of the second transistor is electrically connected to the fifth wiring,
wherein the first wiring and the second wiring are arranged in parallel to each other,
wherein the third wiring, the fourth wiring, and the fifth wiring are arranged in parallel to each other,
wherein the first wiring is arranged to intersect with the fourth wiring,
wherein each of the first and second transistors is an n-channel transistor, and
wherein each of the first and second transistors comprises a metal oxide in a channel formation region.

### Claim 2

A memory device comprising:
m×n (each of m and n is an integer greater than or equal to 1) memory cells;
n first wirings;
n second wirings;
m third wirings;
m fourth wirings; and
m fifth wirings,
wherein the m×n memory cells are arranged in a matrix,
wherein each of the memory cells is electrically connected to the first to fifth wirings,
wherein each of the memory cells comprises first and second transistors,
wherein the second transistor comprises a front gate and a back gate,
wherein one of a source and a drain of the first transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to the front gate of the second transistor,
wherein a gate of the first transistor is electrically connected to the third wiring,
wherein one of a source and a drain of the second transistor is electrically connected to the second wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to the fourth wiring,
wherein the back gate of the second transistor is electrically connected to the fifth wiring,
wherein the first wiring and the second wiring are arranged in parallel to each other,
wherein the third wiring, the fourth wiring, and the fifth wiring are arranged in parallel to each other,
wherein the first wiring is arranged to intersect with the fourth wiring,
wherein each of the first and second transistors is an n-channel transistor, and
wherein each of the first and second transistors comprises a metal oxide in a channel formation region.

### Claim 3

A memory device comprising:
a memory cell array; and
a peripheral circuit,
wherein the memory cell array comprises m×n (each of m and n is an integer greater than or equal to 1) memory cells, n first wirings, n second wirings, m third wirings, and m fourth wirings,
wherein the m×n memory cells are arranged in a matrix,
wherein each of the memory cells is electrically connected to the first to fourth wirings,
wherein each of the memory cells comprises first and second transistors,
wherein one of a source and a drain of the first transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor,
wherein a gate of the first transistor is electrically connected to the third wiring,
wherein one of a source and a drain of the second transistor is electrically connected to the second wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to the fourth wiring,
wherein each of the first transistor and the second transistor is an n-channel transistor,
wherein each of the first transistor and the second transistor comprises a metal oxide in a channel formation region,
wherein the peripheral circuit comprises a first circuit, a second circuit, and a controller,
wherein the first circuit is electrically connected to the first wiring and the second wiring,
wherein the first circuit is configured to write data to the memory cell and is configured to read data from the memory cell,
wherein the second circuit is electrically connected to the third wiring and the fourth wiring,
wherein the second circuit is configured to drive the third wiring and the fourth wiring, and
wherein the controller is configured to control the first circuit and the second circuit.

### Claim 4 (depends on 3)

The memory device according to claim 3,
wherein each of the memory cells comprises a capacitor,
wherein one electrode of the capacitor is electrically connected to the gate of the second transistor, and
wherein the other electrode of the capacitor is electrically connected to a wiring supplied with a predetermined potential.

### Claim 5 (depends on 3)

The memory device according to claim 3,
wherein the first circuit supplies a first potential or a second potential to the first wiring and the second wiring,
wherein the second circuit supplies the first potential or the second potential to the fourth wiring, and
wherein the second circuit supplies the first potential or a third potential to the third wiring.

### Claim 6 (depends on 3)

The memory device according to claim 3,
wherein each of the first circuit and the second circuit comprises a transistor formed on a semiconductor substrate, and
wherein the first transistor and the second transistor are stacked above the semiconductor substrate.

### Claim 7

A memory device comprising:
a memory cell array; and
a peripheral circuit,
wherein the memory cell array comprises m×n (each of m and n is an integer greater than or equal to 1) memory cells, n first wirings, n second wirings, m third wirings, and m fourth wirings,
wherein the m×n memory cells are arranged in a matrix,
wherein each of the memory cells is electrically connected to the first to fourth wirings,
wherein each of the memory cells comprises first and second transistors,
wherein one of a source and a drain of the first transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor,
wherein a gate of the first transistor is electrically connected to the third wiring,
wherein one of a source and a drain of the second transistor is electrically connected to the second wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to the fourth wiring,
wherein each of the first transistor and the second transistor is an n-channel transistor,
wherein each of the first transistor and the second transistor comprises a metal oxide in a channel formation region,
wherein the peripheral circuit comprises a first circuit, a second circuit, and a controller,
wherein the first circuit is electrically connected to the first wiring and the second wiring,
wherein the first circuit is configured to write data to the memory cell and is configured to read data from the memory cell,
wherein the second circuit is electrically connected to the third wiring and the fourth wiring,
wherein the second circuit is configured to drive the third wiring and the fourth wiring,
wherein the controller is configured to control the first circuit and the second circuit, and
wherein the controller is configured to be a serial peripheral interface.

### Claim 8

A memory device comprising:
a memory cell array; and
a peripheral circuit,
wherein the memory cell array comprises m×n (each of m and n is an integer greater than or equal to 1) memory cells, n first wirings, n second wirings, m third wirings, and m fourth wirings,
wherein the m×n memory cells are arranged in a matrix,
wherein each of the memory cells is electrically connected to the first to fourth wirings,
wherein each of the memory cells comprises first and second transistors,
wherein one of a source and a drain of the first transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor,
wherein a gate of the first transistor is electrically connected to the third wiring,
wherein one of a source and a drain of the second transistor is electrically connected to the second wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to the fourth wiring,
wherein each of the first transistor and the second transistor is an n-channel transistor,
wherein each of the first transistor and the second transistor comprises a metal oxide in a channel formation region,
wherein the peripheral circuit comprises a first circuit, a second circuit, a controller, and a page buffer,
wherein the first circuit is electrically connected to the first wiring and the second wiring,
wherein the page buffer is configured to store data temporarily,
wherein the controller is configured to write data to the page buffer and is configured to read data from the page buffer,
wherein the first circuit is configured to write data read from the page buffer, to the memory cell and is configured to write data read from the memory cell, to the page buffer,
wherein the second circuit is electrically connected to the third wiring and the fourth wiring,
wherein the second circuit is configured to drive the third wiring and the fourth wiring,
wherein the controller is configured to control the first circuit and the second circuit, and
wherein the controller is configured to be a serial peripheral interface.