# US 11,309,426 B2 · Pillar-shaped semiconductor device having connection material layer for anchoring wiring conductor layer and method for producing the same

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- Number: US 11,309,426 B2
- Document ID: US11309426B2
- Status: Granted
- Kind: B2
- Application number: 16/580,510
- Filed: 2019-09-24
- Published: 2020-01-16
- Granted: 2022-04-19
- Earliest claimed: 2017-03-27
- Assignees: Unisantis Electronics Singapore Pte. Ltd.
- Applicants: Unisantis Electronics Singapore Pte. Ltd.
- Inventors: Fujio Masuoka; Nozomu Harada
- Web page: https://patentgrep.com/patent/US11309426B2

## CPC

- H10D 30/6728: {Vertical TFTs}
- H10P 32/1414: {the applied layer being silicon, silicide or SIPOS, e.g. polysilicon or porous silicon}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/6729: {characterised by the electrodes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 64/01: Manufacture or treatment
- H10D 64/252: {for vertical or pseudo-vertical devices}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0195: {the components including vertical IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 88/01: {Manufacture or treatment}
- H10P 32/14: within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
- H10P 32/171: {being group IV material}
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

An SGT circuit includes a first conductor layer which contains a semiconductor atom, which is in contact with an N+ region and a P+ region of a Si pillar, or a TiN layer, and whose outer circumference is located outside an outer circumference of a SiO2 layer in plan view, and a second conductor layer which contains a metal atom, which is connected to an outer periphery of the first conductor layer, and which extends in a horizontal direction.

## Claims

### Claim 1

A method for producing a pillar-shaped semiconductor device, comprising:
(a) forming, on a substrate, a semiconductor pillar that stands in a first direction perpendicular to a surface of the substrate;
(b) forming, so as to surround the semiconductor pillar, a first material layer either inclusive or exclusive of a gate conductor layer, wherein the outermost layer of the first material layer, which is single- or multi-layered, is surrounded by a first insulating layer;
(c) forming, so as to surround the first material layer, a second insulating layer having an upper surface positioned lower than a top portion of the semiconductor pillar;
(d) removing a part of the first material layer to expose a side surface of the semiconductor pillar or of the gate conductor layer to form an opening in the first material layer so that a lower end of the opening is positioned as high as the upper surface of the second insulating layer in the first direction;
(e) forming a connection material layer, which contains a semiconductor atom or a metal atom, such that the connection material layer is in contact with the exposed side surface of the semiconductor pillar or of the gate conductor layer, wherein the connection material layer has an outer circumference extensive in a second direction perpendicular to the first direction beyond an outer circumference of the first material layer, and the connection material layer is formed by a selective deposition method so that the connection material layer is selectively deposited on the exposed side surface of the semiconductor pillar or of the side surface of the gate conductor layer but not deposited on a surface of the first insulating layer or a surface of the second insulating layer; and
(f) forming a wiring conductor layer over the second insulating layer so that the wiring conductor layer at least partially surrounds the connection material layer,
(g) wherein the connection material layer is formed such that a gap is formed in the opening between an upper surface of the connection material layer and an upper surface of the opening.

### Claim 2 (depends on 1)

The method for producing a pillar-shaped semiconductor device according to claim 1, wherein the semiconductor pillar includes a donor or acceptor impurity region inside thereof, and forming the connection material layer comprises forming the connection material layer in contact with a side surface of the impurity region of the semiconductor pillar.

### Claim 3 (depends on 1)

The method for producing a pillar-shaped semiconductor device according to claim 1, wherein forming a connection material layer by the selective deposition method comprises forming the connection material layer that contains a donor or acceptor impurity or forming the connection material layer and subsequently adding the donor or acceptor impurity to the formed connection material layer, and
the method further comprises diffusing the donor or acceptor impurity into the semiconductor pillar by heat treatment.

### Claim 4 (depends on 1)

The method for producing a pillar-shaped semiconductor device according to claim 1, wherein at least a part of the connection material layer, which is in contact with the semiconductor pillar, comprises a semiconductor layer, and the method further comprises alloying the semiconductor layer by heat treatment.

### Claim 5 (depends on 1)

The method for producing a pillar-shaped semiconductor device according to claim 1, wherein at least one of the connection material layer and the wiring conductor layer contains a metal atom, and the method further comprises diffusing the metal atom into the semiconductor pillar by heat treatment.

### Claim 6 (depends on 1)

The method for producing a pillar-shaped semiconductor device according to claim 1, wherein forming a wiring conductor layer includes forming a wiring conductor layer that contains a donor or acceptor impurity, and the method further comprises diffusing the donor or acceptor impurity inside of the semiconductor pillar by heat treatment.

### Claim 7 (depends on 1)

The method for producing a pillar-shaped semiconductor device according to claim 1, wherein forming a semiconductor pillar includes forming a semiconductor pillar having therein a third insulating layer that insulates an upper portion and a lower portion of the semiconductor pillar from each other, and the method further comprises forming a donor or acceptor impurity region in the semiconductor pillar above and below the third insulating layer.

### Claim 8 (depends on 7)

The method for producing a pillar-shaped semiconductor device according to claim 7, comprising removing a part of the gate conductor layer that surrounds an outer periphery of the donor or acceptor impurity region.