# US 11,309,425 B2 · Field effect transistor having source control electrode, manufacturing method thereof and electronic device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,309,425 B2 - Document ID: US11309425B2 - Status: Granted - Kind: B2 - Application number: 16/772,751 - Filed: 2018-10-17 - Published: 2020-10-08 - Granted: 2022-04-19 - Earliest claimed: 2017-12-14 - Assignees: Beijing Hua Tan Yuan Xin Electronics Technology Co., Ltd; Beijing Huatan Technology Co., Ltd. - Applicants: Beijing Hua Tan Yuan Xin Electronics Technology Co., Ltd; Beijing Huatan Technology Co., Ltd. - Inventors: Shibo Liang - Web page: https://patentgrep.com/patent/US11309425B2 ## CPC - H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes} - H10D 12/021: {of gated diodes, e.g. field-controlled diodes [FCD]} - H10D 12/211: {Gated diodes} - H10D 30/017: {of FETs having two-dimensional material channels, e.g. TMD FETs} - H10D 30/031: {of thin-film transistors [TFT]} - H10D 30/6737: {characterised by the electrode materials} - H10D 30/6743: {Silicon} - H10D 62/121: {oriented parallel to substrates} - H10D 64/62: Electrodes ohmically coupled to a semiconductor - H10K 10/462: {Insulated gate field-effect transistors [IGFETs]} - B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES - B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES ## Abstract A field effect transistor, a method of manufacturing the field effect transistor, and an electronic device are provided, wherein the field effect transistor comprises: a source(105) formed of a Dirac material(103) and a drain(107); a channel(102) disposed between the source(105) and the drain(107); and a source control electrode(108) disposed on the source(105) and for controlling the doping of the Dirac material(103) such that the Dirac material(103) and the channel(102) are doped in an opposite manner; and a gate(106) disposed on the channel(102) and electrically insulated from the channel(102). ## Claims ### Claim 1 A field effect transistor having a source control electrode, comprises: a source and a drain, the source being formed of a Dirac material; a channel disposed between the source and the drain; a source electrode and the source control electrode that are disposed on the source, wherein the source control electrode is configured to apply a voltage on the Dirac material of the source to control doping of the Dirac material such that the Dirac material and the channel are doped opposite; and a gate disposed on the channel and electrically insulated from the channel. ### Claim 2 (depends on 1) The field effect transistor having a source control electrode according to claim 1, wherein the Dirac material comprises: a single layer of graphene, a Weyl semimetal, a d-wave superconductor, or a topological insulator. ### Claim 3 (depends on 1) The field effect transistor having a source control electrode according to claim 1, wherein the source is in electrical contact with the channel. ### Claim 4 (depends on 3) The field effect transistor having a source control electrode according to claim 3, wherein the source control electrode is configured to cause the contact barrier height between the source and the channel to be less than 0.2 electron volts. ### Claim 5 (depends on 1) The field effect transistor having a source control electrode according to claim 1, wherein, the channel is p-type doped, and the source control electrode is configured to cause the Dirac material to be n-type doped; or the channel is n-doped, and the source control electrode is configured to cause the Dirac material to be p-type doped. ### Claim 6 (depends on 1) The field effect transistor having a source control electrode according to claim 1, further comprises a gate insulating layer formed on the channel and having an equivalent oxide thickness less than 2 nm. ### Claim 7 (depends on 1) The field effect transistor having a source control electrode according to claim 1, further comprises a source control electrode insulating layer formed between the source and the source control electrode. ### Claim 8 (depends on 6) The field effect transistor having a source control electrode according to claim 6, further comprising a source control electrode insulating layer formed between the source and the source control electrode, the source control electrode insulating layer and the gate insulating layer being formed of the same layer of material. ### Claim 9 (depends on 1) The field effect transistor having a source control electrode according to claim 1, wherein the drain and the channel are formed of the same layer of material. ### Claim 10 (depends on 1) The field effect transistor having a source control electrode according to claim 1, wherein the drain is formed of the Dirac material. ### Claim 11 (depends on 1) The field effect transistor having a source control electrode according to claim 1, wherein the channel is formed of at least one of carbon nanotubes, semiconductor nanowires, two-dimensional semiconductor materials, or three-dimensional semiconductor materials. ### Claim 12 A method for manufacturing a field effect transistor having a source control electrode, comprises: forming a channel on a substrate; forming a source and a drain on the substrate such that the channel is located between the source and the drain, the source being formed of a Dirac material; forming a source electrode on the source; forming, on the source, a source control electrode that is configured to apply a voltage on the Dirac material to control doping of the Dirac material such that the Dirac material and the channel are doped in an opposite manner; and forming a gate on the channel such that a projection of the gate on the substrate overlaps with a projection of the channel on the substrate, and the gate and the channel are electrically insulated. ### Claim 13 (depends on 12) The method according to claim 12, wherein the Dirac material comprises: a single layer of graphene, a Weyl semimetal, a d-wave superconductor, or a topological insulator. ### Claim 14 (depends on 12) The method according to claim 12, wherein the step of forming a source and a drain on the substrate further comprises electrically contacting the source with the channel. ### Claim 15 (depends on 14) The method according to claim 14, wherein the source control electrode is configured to cause the contact barrier height between the source and the channel to be less than 0.2 electron volts. ### Claim 16 (depends on 12) The method according to claim 12, wherein, the channel is p-type doped, and the source control electrode is configured to cause the Dirac material to be n-type doped; or the channel is n-doped, and the source control electrode is configured to cause the Dirac material to be p-type doped. ### Claim 17 (depends on 12) The method according to claim 12, further comprises: forming a gate insulating layer on the channel, the gate insulating layer having an equivalent oxide thickness less than 2 nm. ### Claim 18 (depends on 12) The method according to claim 12, further comprises: forming a source control electrode insulating layer over the source, the source control electrode insulating layer being disposed between the source and the source control electrode. ### Claim 19 (depends on 17) The method according to claim 17, further comprises: forming a source control electrode insulating layer over the source, the source control electrode insulating layer being formed between the source and the source control electrode, and the source control electrode insulating layer and the gate insulating layer being formed of the same layer of material. ### Claim 20 (depends on 12) The method according to claim 12, wherein the drain and the channel are formed of the same layer of material. ### Claim 21 (depends on 12) The method according to claim 12, wherein the drain is formed of the Dirac material. ### Claim 22 (depends on 12) The method according to claim 12, wherein the channel is formed of at least one of carbon nanotubes, semiconductor nanowires, two dimensional semiconductor materials, or three-dimensional semiconductor materials. ### Claim 23 An electronic device comprising a field effect transistor having a source control electrode, the field effect transistor having a source control electrode comprising: a source and a drain, the source being formed of a Dirac material; a channel disposed between the source and the drain; a source electrode and a source control electrode that are disposed on the source, wherein the source control electrode is configured to apply a voltage on the Dirac material of the source to control doping of the Dirac material such that the Dirac material and the channel are doped in an opposite manner; and a gate disposed on the channel and electrically insulated from the channel.