# US 11,309,422 B2 · Semiconductor structure and method for forming the same

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- Number: US 11,309,422 B2
- Document ID: US11309422B2
- Status: Granted
- Kind: B2
- Application number: 16/862,987
- Filed: 2020-04-30
- Published: 2021-02-04
- Granted: 2022-04-19
- Earliest claimed: 2019-07-30
- Assignees: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Applicants: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Inventors: Fei Zhou
- Web page: https://patentgrep.com/patent/US11309422B2

## CPC

- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/0191: {forming stacked channels, e.g. changing their shapes or sizes}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/506: {having different thicknesses, sizes or shapes}
- H10D 62/112: {for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 64/251: {Source or drain electrodes for field-effect devices}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A semiconductor structure and a method for forming the same are provided. One form of the method includes: providing a base, where a channel stack and a tear-off structure span the channel stack being formed on the base, and the channel stack including a sacrificial layer and a channel layer; forming a groove in channel stacks on both sides of a gate structure; laterally etching the sacrificial layer exposed from the groove to form a remaining sacrificial layer; forming a source/drain doped region in the channel layer exposed from the remaining sacrificial layer; forming an interlayer dielectric layer on the base; etching the interlayer dielectric layer on one side of the source region to expose a surface of the channel layer corresponding to the source region; etching the interlayer dielectric layer on one side of the drain region to expose the surface of the channel layer corresponding to the drain region; forming a first metal silicide layer on a surface of the channel layer corresponding to the source region; forming a second metal silicide layer on a surface of the channel layer corresponding to the drain region; forming a first conductive plug covering the first metal silicide layer and a second conductive plug covering the second metal silicide layer. In the present disclosure, contact resistance of the first conductive plug, the second conductive plug, and the source/drain doped region is reduced.

## Claims

### Claim 1

A method for forming a semiconductor structure, comprising:
providing a base, where one or more stacked channel stacks is formed on the base, the channel stack comprises a sacrificial layer and a channel layer located on the sacrificial layer, a gate structure is formed on the base, and the gate structure spans the channel stack and covers a portion of a top and a portion of a side wall of the channel stack;
forming, in the channel stack on both sides of the gate structure, a groove exposing the base;
laterally etching, along a direction perpendicular to a side wall of the gate structure, a portion of the sacrificial layer exposed from the groove, to form a remaining sacrificial layer under the gate structure;
forming a source/drain doped region in the channel layer exposed from the remaining sacrificial layer, wherein the source/drain doped region located on one side of the gate structure serves as a source region, and the source/drain doped region located on the other side of the gate structure serves as a drain region;
forming an interlayer dielectric layer on the base exposed from the gate structure after the source/drain doped region is formed, the interlayer dielectric layer covering a side wall of the gate structure;
etching the interlayer dielectric layer on one side of the source region to expose each surface of the channel layer corresponding to the source region;
etching the interlayer dielectric layer on one side of the drain region to expose each surface of the channel layer corresponding to the drain region;
forming a first metal silicide layer on a surface of the channel layer corresponding to the source region exposed from the interlayer dielectric layer;
forming a second metal silicide layer on a surface of the channel layer corresponding to the drain region exposed from the interlayer dielectric layer;
forming a first conductive plug on a base on one side of the source region, the first conductive plug further covering the first metal silicide layer; and
forming a second conductive plug on a base on one side of the drain region, the second conductive plug further covering the second metal silicide layer.

### Claim 2 (depends on 1)

The method for forming the semiconductor structure according to claim 1, wherein:
the step of forming the source/drain doped region comprises: forming a doped epitaxial layer in the groove, the doped epitaxial layer covering a surface of the channel layer exposed from the remaining sacrificial layer, and doped ions in the doped epitaxial layer diffusing into the channel layer, to form the source/drain doped region in the channel layer; and
in the step of forming the interlayer dielectric layer on the base exposed from the gate structure, the interlayer dielectric layer covers the source/drain doped region.

### Claim 3 (depends on 2)

The method for forming the semiconductor structure according to claim 2, wherein the step of forming the doped epitaxial layer in the groove comprises: forming an epitaxial layer in the groove, and performing in-situ self-doping during forming of the epitaxial layer.

### Claim 4 (depends on 2)

The method for forming the semiconductor structure according to claim 2, wherein:
the interlayer dielectric layer and the doped epitaxial layer on one side of the source region are etched in sequence, to expose each surface of the channel layer corresponding to the source region; and
the interlayer dielectric layer and the doped epitaxial layer on one side of the drain region are etched in sequence, to expose each surface of the channel layer corresponding to the drain region.

### Claim 5 (depends on 4)

The method for forming the semiconductor structure according to claim 4, wherein:
in the step of etching the doped epitaxial layer on one side of the source region, the doped epitaxial layer is removed, or a portion of the doped epitaxial layer is removed to reduce its width; and
in the step of etching the doped epitaxial layer on one side of the drain region, the doped epitaxial layer is removed, or a portion of the doped epitaxial layer is removed to reduce its width.

### Claim 6 (depends on 2)

The method for forming the semiconductor structure according to claim 2, wherein:
in the step of forming the doped epitaxial layer, the doped epitaxial layer has a first preset doping concentration;
in the step of forming the source/drain doped region, the source/drain doped region has a second preset doping concentration; and
the first preset doping concentration is 1.5 times to 5 times of the second preset doping concentration.

### Claim 7 (depends on 4)

The method for forming the semiconductor structure according to claim 4, wherein in the step of etching the doped epitaxial layer, a portion of the doped epitaxial layer is removed to reduce the doped epitaxial layer in width.

### Claim 8 (depends on 1)

The method for forming the semiconductor structure according to claim 1, wherein:
the interlayer dielectric layer on one side of the source region and the interlayer dielectric layer on one side of the drain region are etched in a same step,
the first metal silicide layer and the second metal silicide are formed in a same step, and
the first conductive plug and the second conductive plug are formed in a same step.

### Claim 9 (depends on 8)

The method for forming the semiconductor structure according to claim 8, wherein:
in the step of etching the doped epitaxial layer on one side of the source region, the doped epitaxial layer is removed;
in the step of etching the doped epitaxial layer on one side of the drain region, the doped epitaxial layer is removed;
the method further comprises: after the first metal silicide layer and the second metal silicide layer are formed, and before the first conductive plug and the second conductive plug are formed, forming a capping dielectric layer on a base exposed from the interlayer dielectric layer; and
in the step of forming the first conductive plug and the second conductive plug, the first conductive plug and the second conductive plug are formed in the capping dielectric layer.

### Claim 10 (depends on 1)

The method for forming the semiconductor structure according to claim 1, wherein:
after the first conductive plug is formed, the interlayer dielectric layer on one side of the drain region is etched; or
after the second conductive plug is formed, the interlayer dielectric layer on one side of the source region is etched.

### Claim 11 (depends on 1)

The method for forming the semiconductor structure according to claim 1, wherein:
in the step of forming the first metal silicide layer, the first metal silicide layer has a first thickness;
in the step of forming the second metal silicide layer, the second metal silicide layer has a second thickness; and
the first thickness is greater than the second thickness.

### Claim 12 (depends on 1)

The method for forming the semiconductor structure according to claim 1, wherein the method further comprises:
before forming the source/drain doped region, forming a barrier layer on a side wall of the remaining sacrificial layer, where the barrier layer has a thickness that is smaller than a length of the channel layer exposed from the remaining sacrificial layer.

### Claim 13 (depends on 12)

The method for forming the semiconductor structure according to claim 12, wherein:
the step of forming the barrier layer comprises: forming an initial barrier layer on the side wall of the remaining sacrificial layer, where a side wall of the initial barrier layer is flush with a side wall of the channel layer exposed from the remaining sacrificial layer; and
laterally etching a portion of the initial barrier layer in thickness along a direction perpendicular to the side wall of the gate structure, where the remaining initial barrier layer serves as the barrier layer.

### Claim 14 (depends on 13)

The method for forming the semiconductor structure according to claim 13, wherein:
in the step of providing the base, a spacer is formed on the side wall of the gate structure;
the step of forming the groove comprises: etching channel stacks on both sides of the gate structure using the spacer as a mask; and
in the step of laterally etching the portion of the initial barrier layer in thickness, laterally etching a portion of the spacer in thickness.

### Claim 15 (depends on 13)

The method for forming the semiconductor structure according to claim 13, wherein the portion of the initial barrier layer in thickness is laterally etched using an isotropic dry etching process.

### Claim 16 (depends on 1)

The method for forming the semiconductor structure according to claim 1, wherein a process for forming any of the first metal silicide layer and the second metal silicide layer comprises an atomic layer deposition process.