# US 11,309,421 B2 · Semiconductor devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,309,421 B2 - Document ID: US11309421B2 - Status: Granted - Kind: B2 - Application number: 16/816,971 - Filed: 2020-03-12 - Published: 2020-07-09 - Granted: 2022-04-19 - Earliest claimed: 2017-11-17 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Jung-Gil Yang; Beom-Jin Park; Seung-Min Song; Geum-Jong Bae; Dong-Il Bae - Web page: https://patentgrep.com/patent/US11309421B2 ## CPC - B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic - H10D 30/62: Fin field-effect transistors [FinFET] - H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability} - H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels - H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around} - H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)} - H10D 62/115: {Dielectric isolations, e.g. air gaps} - H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions} - H10D 62/121: {oriented parallel to substrates} - H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)} - H10D 62/364: {of IGFETs} - H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions - H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes} - H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers} - H10D 64/518: {characterised by their lengths or sectional shapes} - H10D 84/0158: {the components including FinFETs} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask} - H10W 10/011: {of isolation regions comprising dielectric materials} - H10W 10/10: Isolation regions comprising dielectric materials - H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels} - H10D 30/507: {characterised by inner spacers between adjacent channels} - B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device includes channels, a gate structure, and a source/drain layer. The channels are disposed at a plurality of levels, respectively, and spaced apart from each other in a vertical direction on an upper surface of a substrate. The gate structure is disposed on the substrate, at least partially surrounds a surface of each of the channels, and extends in a first direction substantially parallel to the upper surface of the substrate. The source/drain layer is disposed at each of opposite sides of the gate structure in a second direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the first direction and is connected to sidewalls of the channels. A length of the gate structure in the second direction changes along the first direction at a first height from the upper surface of the substrate in the vertical direction. ## Claims ### Claim 1 A semiconductor device comprising: channels at a plurality of levels, respectively, the channels spaced apart from each other in a vertical direction on an upper surface of a substrate; a gate structure on the substrate, the gate structure at least partially surrounding a surface of each of the channels and extending in a first direction substantially parallel to the upper surface of the substrate; a source/drain layer at each of opposite sides of the gate structure in a second direction substantially parallel to the upper surface of the substrate and crossing the first direction, the source/drain layer being connected to sidewalls of the channels; a first spacer on each of opposite sidewalls of an upper portion of the gate structure in the second direction, the upper portion of the gate structure being on an upper surface of an uppermost one of the channels and overlapping the channels in the vertical direction; and a second spacer on each of opposite sidewalls of a lower portion of the gate structure in the second direction, the lower portion of the gate structure being between the channels and between the substrate and a lowermost one of the channels, and overlapping the channels in the vertical direction, wherein at a first height from the upper surface of the substrate in the vertical direction, a minimum value of a length in the second direction of a first portion of the gate structure overlapping the channels in the vertical direction is less than a length in the second direction of a second portion of the gate structure not overlapping the channels in the vertical direction, wherein at the first height, a length in the second direction of a third portion of the gate structure close to the channels is greater than a length in the second direction of a fourth portion of the gate structure far from the channels, the third portion and the fourth portion of the gate structure being in the second portion of the gate structure, and wherein, at the first height, the length in the second direction of the first portion of the gate structure increases as the first portion becomes closer to the second portion of the gate structure. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein at a height below the upper surface of the uppermost one of the channels, the length in the second direction of the third portion of the gate structure increases as the height below the upper surface of the uppermost one of the channels decreases. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein the first height is lower than the upper surface of the uppermost one of the channels. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein, at a height above the upper surface of the uppermost one of the channels, the length in the second direction of the first portion of the gate structure is substantially constant along the vertical direction. ### Claim 5 (depends on 1) The semiconductor device of claim 1, wherein the channels are spaced apart from each other in the first direction at each level, and at the first height, the length of the gate structure in the second direction changes periodically along the first direction. ### Claim 6 (depends on 1) The semiconductor device of claim 1, wherein the second spacer has a vertical cross-section having a horseshoe shape convex toward a central portion of the lower portion of the gate structure in the second direction. ### Claim 7 (depends on 6) The semiconductor device of claim 6, wherein each of the first and second spacers contacts the source/drain layer, and an air gap is formed between the second spacer and the source/drain layer. ### Claim 8 (depends on 1) The semiconductor device of claim 1, wherein the gate structure further includes a lateral portion not overlapping the channels in the vertical direction, and the first spacer covers each of opposite sidewalls of the lateral portion of the gate structure in the second direction. ### Claim 9 (depends on 8) The semiconductor device of claim 8, wherein the first spacer has a slanted sidewall with respect to the upper surface of the substrate at a height below the upper surface of the uppermost one of the channels. ### Claim 10 (depends on 1) The semiconductor device of claim 1, wherein a first thickness of the first spacer in the second direction is equal to or smaller than a second thickness in the second direction of a central portion of the second spacer in the vertical direction. ### Claim 11 (depends on 1) The semiconductor device of claim 1, wherein the first and second directions are substantially perpendicular to each other. ### Claim 12 A semiconductor device comprising: channels at a plurality of levels, respectively, the channels spaced apart from each other in a vertical direction on an upper surface of a substrate; a gate structure on the substrate, the gate structure at least partially surrounding a surface of each of the channels and extending in a first direction substantially parallel to the upper surface of the substrate; a source/drain layer at each of opposite sides of the gate structure in a second direction substantially parallel to the upper surface of the substrate and crossing the first direction, the source/drain layer being connected to sidewalls of the channels; a first spacer on each of opposite sidewalls of an upper portion of the gate structure in the second direction, the upper portion of the gate structure being on an upper surface of an uppermost one of the channels and overlapping the channels in the vertical direction; and a second spacer on each of opposite sidewalls of a lower portion of the gate structure in the second direction, the lower portion of the gate structure being between the channels and between the substrate and a lowermost one of the channels, and overlapping the channels in the vertical direction, wherein at a first height from the upper surface of the substrate in the vertical direction, a minimum value of a length in the second direction of a first portion of the gate structure overlapping the channels in the vertical direction is less than a length in the second direction of a second portion of the gate structure not overlapping the channels in the vertical direction, wherein at the first height, a length in the second direction of a third portion of the gate structure close to the channels is greater than a length in the second direction of a fourth portion of the gate structure far from the channels, the third portion and the fourth portion of the gate structure being in the second portion of the gate structure, wherein, at the first height, the length in the second direction of the first portion of the gate structure increases as the first portion becomes closer to the second portion of the gate structure, and wherein the second spacer has a vertical cross-section having a horseshoe shape convex toward a central portion of the lower portion of the gate structure in the second direction. ### Claim 13 (depends on 12) The semiconductor device of claim 12, wherein each of the first and second spacers contacts the source/drain layer, and an air gap is formed between the second spacer and the source/drain layer. ### Claim 14 (depends on 12) The semiconductor device of claim 12, wherein the gate structure further includes a lateral portion not overlapping the channels in the vertical direction, and the first spacer covers each of opposite sidewalls of the lateral portion of the gate structure in the second direction. ### Claim 15 (depends on 12) The semiconductor device of claim 12, wherein the first spacer has a slanted sidewall with respect to the upper surface of the substrate at a height below the upper surface of the uppermost one of the channels. ### Claim 16 (depends on 12) The semiconductor device of claim 12, wherein a first thickness of the first spacer in the second direction is equal to or smaller than a second thickness in the second direction of a central portion of the second spacer in the vertical direction. ### Claim 17 A semiconductor device comprising: an active region on a substrate; channels at a plurality of levels, respectively, the channels spaced apart from each other in a vertical direction on the active region; a gate structure on the substrate, the gate structure at least partially surrounding a surface of each of the channels and extending in a first direction substantially parallel to the upper surface of the substrate, and the gate structure including a gate insulation pattern and a gate electrode sequentially stacked from a surface of each of the channels; a source/drain layer at each of opposite sides of the gate structure in a second direction substantially parallel to the upper surface of the substrate and crossing the first direction, the source/drain layer being connected to sidewalls of the channels; a first spacer on each of opposite sidewalls of an upper portion of the gate structure in the second direction, the upper portion of the gate structure being on an upper surface of an uppermost one of the channels and overlapping the channels in the vertical direction; and a second spacer on each of opposite sidewalls of a lower portion of the gate structure in the second direction, the lower portion of the gate structure being between the channels and between the substrate and a lowermost one of the channels, and overlapping the channels in the vertical direction, wherein at a first height from the upper surface of the substrate in the vertical direction, a minimum value of a length in the second direction of a first portion of the gate structure overlapping the channels in the vertical direction is less than a length in the second direction of a second portion of the gate structure not overlapping the channels in the vertical direction, wherein at the first height, a length in the second direction of a third portion of the gate structure close to the channels is greater than a length in the second direction of a fourth portion of the gate structure far from the channels, the third portion and the fourth portion of the gate structure being in the second portion of the gate structure, and wherein, at the first height, the length in the second direction of the first portion of the gate structure increases as the first portion becomes closer to the second portion of the gate structure. ### Claim 18 (depends on 17) The semiconductor device of claim 17, wherein the gate structure further includes an interface pattern between the surface of each of the channels and the gate insulation pattern, the interface pattern including silicon oxide and the gate insulation pattern including a metal oxide. ### Claim 19 (depends on 17) The semiconductor device of claim 17, wherein at a height below the upper surface of the uppermost one of the channels, the length in the second direction of the third portion of the gate structure increases as the height below the upper surface of the uppermost one of the channels decreases. ### Claim 20 (depends on 17) The semiconductor device of claim 17, wherein the channels are spaced apart from each other in the first direction at each level, and at the first height, the length of the gate structure in the second direction changes periodically along the first direction.