# US 11,309,420 B2 · Semiconductor device and fabrication method thereof

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- Number: US 11,309,420 B2
- Document ID: US11309420B2
- Status: Granted
- Kind: B2
- Application number: 16/795,864
- Filed: 2020-02-20
- Published: 2020-08-27
- Granted: 2022-04-19
- Earliest claimed: 2019-02-25
- Assignees: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Applicants: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Inventors: Haiyang Zhang; Bo Su
- Web page: https://patentgrep.com/patent/US11309420B2

## CPC

- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10P 50/242: {of Group IV materials}
- H10P 50/267: {using plasmas}
- H10P 50/268: {of silicon-containing layers}
- H10P 50/287: {by chemical means}
- H10P 50/71: {using masks for conductive or resistive materials}
- H10P 50/73: {using masks for insulating materials}
- H10P 76/408: {characterised by their sizes, orientations, dispositions, behaviours or shapes}
- H10P 76/4083: {characterised by their behaviours during the lithography processes, e.g. soluble masks or redeposited masks}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

The present disclosure provides a semiconductor device and a fabrication method. The method includes: providing a substrate having fins and forming an initial gate structure across the fins, which covers a portion of a top surface and sidewall surfaces of the fins, and includes an initial first region and an initial second region on the initial first region. A bottom boundary of the initial second region is higher than the top surface of the fins, and a size of the initial first region is larger than a size of the initial second region. A first etching process is performed on sidewalls of the initial gate structure to form a gate structure, which includes a first region formed by etching the initial first region, and a second region formed by etching the initial second region. A size of the first region is smaller than a size of the second region.

## Claims

### Claim 1

A fabrication method of a semiconductor device, comprising:
providing a substrate, having a plurality of fins on a surface of the substrate;
forming an initial gate structure across the plurality of fins, wherein the initial gate structure covers a portion of a top surface and side wall surfaces of the plurality of fins, the initial gate structure includes an initial first region and an initial second region on the initial first region, a bottom boundary of the initial second region is higher than the top surface of the plurality of fins, and a size of the initial first region in an extending direction of the plurality of fins is larger than a size of the initial second region in the extending direction of the plurality of fins; and
performing a first etching process on sidewalls of the initial gate structure to form a gate structure; wherein the gate structure includes a first region formed by etching the initial first region, and a second region formed by etching the initial second region, and a size of the first region in the extending direction of the plurality of fins is smaller than a size of the second region in the extending direction of the plurality of fins.

### Claim 2 (depends on 1)

The method according to claim 1, wherein:
the first region of the gate structure has an inverted trapezoid in a cross section parallel to the extending direction of the plurality of fins and perpendicular to a surface of the substrate.

### Claim 3 (depends on 1)

The method according to claim 1, wherein:
the first etching process is an asynchronous pulse etching process, and
the asynchronous pulse etching process includes:
providing a plasma source;
providing a bias power source;
performing a first-stage etching, wherein the plasma source provides a first source power and the bias power source provides a first bias power in the first-stage etching; and
performing a second-stage etching, wherein the plasma source provides a second source power and the bias power source provides a second bias power in the second-stage etching, the first source power is less than the second source power, and the first bias power is greater than the second bias power.

### Claim 4 (depends on 3)

The method according to claim 3, wherein:
a time length of the first-stage etching is a first time length, a time length of the second-stage etching is a second time length, and a ratio of the first time length to the second time length is about 1% to about 15%.

### Claim 5 (depends on 3)

The method according to claim 3, wherein:
parameters of the asynchronous pulse etching process include:
reaction gases including CH4, O2, Cl2, Ar, CF4, and HBr, wherein:
a flow rate of CH4 is about 5 standard milliliters/minute to about 100 standard mill niters/minute,
a flow rate of O2 is about 5 standard milliliters/minute to about 200 standard milliliters/minute,
a flow rate of Cl2 is about 10 standard milliliters/minute to about 200 standard milliliters/minute,
a flow rate of Ar is about 50 standard milliliters/minute to about 500 standard milliliters/minute,
a flow rate of CF4 is about 0 standard milliliters/minute to about 100 standard milliliters/minute,
a flow rate of HBr is about 50 standard milliliters/minute to about 200 standard milliliters/minute,
a pressure is about 10 mTorr to about 100 mTorr,
a source RF power is about 50 watts to about 1000 watts, and
a bias RF voltage is about 100 volts to about 1000 volts.

### Claim 6 (depends on 1)

The method according to claim 1, wherein:
forming the initial gate structure includes:
forming a gate dielectric material layer on the substrate, and a gate electrode material layer on the gate dielectric material layer; and
patterning the gate dielectric material layer and the gate electrode material layer to form an initial gate dielectric layer and an initial gate electrode layer, wherein the initial gate structure includes the initial gate dielectric layer and the initial gate electrode layer on the initial gate dielectric layer.

### Claim 7 (depends on 6)

The method according to claim 6, wherein:
the initial gate electrode layer is made of one of polysilicon and polycrystalline germanium.

### Claim 8 (depends on 6)

The method according to claim 6, wherein:
before the initial gate structure is formed, the method further includes:
forming an isolation structure on the surface of the substrate, wherein the isolation structure covers a portion of sidewalls of the plurality of fins, a top surface of the isolation structure is lower than the top surface of the plurality of fins, and the initial gate structure is located on a portion of a surface of the isolation structure.

### Claim 9 (depends on 8)

The method according to claim 8, wherein:
before the initial gate structure is formed, the method further includes: forming a mask protection layer on the top surface of the plurality of fins; and
after the isolation structure and the mask protection layer are formed, patterning the gate dielectric material layer and the gate electrode material layer includes:
forming a first mask layer on a surface of the gate electrode material layer, wherein the first mask layer exposes a portion of the surface of the gate electrode material layer;
performing a second etching process to etch the gate electrode material layer, with the first mask layer as a mask, to form an initial gate electrode material layer, wherein a top surface of a portion of the initial gate electrode material layer on two sides of the first mask layer is higher than the top surface of the plurality of fins; and
after the initial gate electrode material layer is formed, performing a third etching process to continuously etch the initial gate electrode material layer and the gate dielectric material layer, with the first mask layer as a mask, until a top surface of the isolation structure and a top surface of the mask protection layer are exposed to form the initial gate structure, wherein the initial gate structure includes the initial gate dielectric layer and the initial gate electrode layer on the initial gate dielectric layer.

### Claim 10 (depends on 9)

The method according to claim 9, wherein:
the second etching process is a dry etching process; and
parameters of the dry etching process include: reaction gases used including SF6, Cl2, O2, CH2F2, and HBr, wherein:
a flow rate of SF6 is about 0 standard milliliters/minute to about 100 standard mill hirers/minute,
a flow rate of Cl2 is about 0 standard milliliters/minute to about 100 standard milliliters/minute,
a flow rate of O2 is about 50 standard milliliters/minute to about 100 standard milliliters/minute,
a flow rate of CH2F2 is about 0 standard milliliters/minute to about 50 standard milliliters/minute;
a flow rate of HBr is about 10 standard milliliters/minute to about 200 standard mill hirers/minute,
a pressure is about 1 mTorr to about 50 mTorr,
a source RF power is about 100 watts to about 1000 watts, and
a bias RF voltage is about 50 volts to about 1200 volts.

### Claim 11 (depends on 9)

The method according to claim 9, wherein:
the mask protection layer is made of one of silicon oxide, silicon nitride, and silicon oxynitride.

### Claim 12 (depends on 9)

The method according to claim 9, wherein:
an etching rate of the mask protection layer by the third etching process is less than an etching rate of the initial gate electrode layer;
the third etching process is a dry etching process; and
parameters of the dry etching process include: reaction gases used including CH4, O2, Cl2, Ar, and CF4, wherein:
a flow rate of CH4 is about 5 standard milliliters/minute to about 100 standard milliliters/minute,
a flow rate of O2 is about 5 standard milliliters/minute to about 200 standard milliliters/minute,
a flow rate of Cl2 is about 10 standard milliliters/minute to about 200 standard milliliters/minute,
a flow rate of Ar is about 50 standard milliliters/minute to about 500 standard milliliters/minute,
a flow rate of CF4 is about 0 standard milliliters/minute to about 100 standard milliliters/minute,
a pressure is about 10 mTorr to about 100 mTorr,
a source RF power is about 100 watts to about 1000 watts, and
a bias voltage is about 100 volts to about 1500 volts.

### Claim 13 (depends on 1)

The method according to claim 1, wherein:
after the gate structure is formed, the method further includes: forming source-drain doped regions in the plurality of fins on both sides of the gate structure; and
forming the source-drain doped regions includes:
forming source-drain openings in the plurality of fins on both sides of the gate structure;
forming an epitaxial layer in the source-drain openings; and
doping source-drain ions in the epitaxial layer to form the source-drain doped regions.