# US 11,309,418 B2 · Contact structure for FinFET semiconductor device

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- Number: US 11,309,418 B2
- Document ID: US11309418B2
- Status: Granted
- Kind: B2
- Application number: 16/417,051
- Filed: 2019-05-20
- Published: 2019-09-12
- Granted: 2022-04-19
- Earliest claimed: 2016-12-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Kun-Mu Li; Liang-Yi Chen; Wen-Chu Hsiao
- Web page: https://patentgrep.com/patent/US11309418B2

## CPC

- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/017: {of FETs having two-dimensional material channels, e.g. TMD FETs}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6215: {having multiple independently-addressable gate electrodes}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/074: {of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers}
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a gate structure formed over a channel region of the semiconductor device, a source/drain region adjacent the channel region, and an electrically conductive contact layer over the source/drain region. The source/drain region includes a first epitaxial layer having a first material composition and a second epitaxial layer formed over the first epitaxial layer. The second epitaxial layer has a second material composition different from the first composition. The electrically conductive contact layer is in contact with the first and second epitaxial layers. A bottom of the electrically conductive contact layer is located below an uppermost portion of the first epitaxial layer.

## Claims

### Claim 1

A semiconductor device, comprising:
a gate structure formed over a channel region of the semiconductor device; and
a source/drain region adjacent the channel region; and
an electrically conductive contact layer disposed over the source/drain region, wherein:
the source drain region comprises:
a first epitaxial layer having a first material composition;
a second epitaxial layer formed over the first epitaxial layer, the second epitaxial layer having a second material composition different from the first composition; and
a capping layer made of a semiconductor material disposed on the second epitaxial layer,
the electrically conductive contact layer is in contact with the first and second epitaxial layers,
the electrically conductive contact layer has a bottom and side faces,
the bottom of the electrically conductive contact layer is located below an uppermost portion of the first epitaxial layer,
part of the side faces contact the second epitaxial layer,
the semiconductor device is a p-type field effect transistor (FET),
the first epitaxial layer comprises Si1-xGex and the second epitaxial layer comprises Si1-yGey, where x<y,
the capping layer is an epitaxial layer comprising Si1-zGez, where 0≤z<0.4, where z<y, and
the capping layer further comprises at least one of B and Ga in an amount of 5.0×1019 atoms/cm3 to 1.0×1021 atoms/cm3.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the first epitaxial layer comprises Si1-xGex, where 0.01<x<0.4.

### Claim 3 (depends on 2)

The semiconductor device according to claim 2, wherein the first epitaxial layer further comprises at least one of B and Ga in an amount of 5.0×1019 atom/cm3 to 1.0×1021 atoms/cm3.

### Claim 4 (depends on 3)

The semiconductor device according to claim 3, wherein the second epitaxial layer comprises Si1-yGey, where 0.2<y<0.8.

### Claim 5 (depends on 4)

The semiconductor device according to claim 4, wherein the second epitaxial layer further comprises at last one of B and Ga in an amount of 1.0×1020 atoms/cm3 to 3.0×1021 atoms/cm3.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein:
the first epitaxial layer and the second epitaxial layer further comprise at least one of B and Ga, and
an amount of at least one of B and Ga in the first epitaxial layer is smaller than an amount of at least one of B and Ga in the second epitaxial layer.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1, wherein an aspect ratio H/W of the first epitaxial layer is in a range from 4 to 20, where H is a height of the first epitaxial layers from an upper surface of an isolation insulating layer and W is a largest width of the first epitaxial layer along a direction in which the gate structure extends.

### Claim 8 (depends on 2)

The semiconductor device according to claim 2, wherein the first epitaxial layer further comprises Ga in an amount of 5.0×1019 atom/cm3 to 1.0×1021 atoms/cm3.

### Claim 9

A semiconductor device including a FinFET, the FinFET comprising:
a first fin structure and a second fin structure disposed over a substrate, upper portions of the first and second fin structures protruding from an isolation insulating layer;
a gate structure over parts of the first and second fin structures;
first epitaxial layers disposed over source/drain regions of the first and second fin structures, respectively, the first epitaxial layers being separated from each other;
a second epitaxial layer disposed over the first epitaxial layers, the second epitaxial layer having a material composition different from the first epitaxial layer;
a first insulating layer disposed over the second epitaxial layer,
an interlayer dielectric (ILD) layer disposed over the first insulating; and
an electrically conductive contact layer in contact with the first and second epitaxial layers,
wherein a bottom of the electrically conductive contact layer is located closer to the substrate than an uppermost portion of the first epitaxial layer,
an entirety of the bottom of the electrically conductive contact layer between the first fin structure and the second fin structure is in contact with the second epitaxial layer, and
a second insulating layer is disposed between a part of the first epitaxial layer and a part of the second epitaxial layer and between the first insulating layer and the isolation insulating layer, and
the second insulating layer is in direct contact with the part of the first epitaxial layer, the first insulating layer and the isolation insulating layer.

### Claim 10 (depends on 9)

The semiconductor device according to claim 9, wherein a void is formed between the second epitaxial layer and the upper surface of the isolation insulating layer.

### Claim 11 (depends on 9)

The semiconductor device according to claim 9, wherein:
the first epitaxial layers comprise Si1-xGex, where 0.01<x<0.4, and
the second epitaxial layer comprises Si1-yGey, where 0.2<y<0.8.

### Claim 12 (depends on 11)

The semiconductor device according to claim 11, further comprising:
a third epitaxial layer disposed over the second epitaxial layer, the third epitaxial layer having a material composition different from the second epitaxial layer.

### Claim 13 (depends on 12)

The semiconductor device according to claim 12, wherein:
the third epitaxial layer comprises Si1-zGez, where x<y and z<y.

### Claim 14 (depends on 12)

The semiconductor device according to claim 12, wherein:
the third epitaxial layer further comprises at least one of B and Ga in an amount of 5.0×1019 atoms/cm3 to 1.0×1021 atoms/cm3.

### Claim 15 (depends on 13)

The semiconductor device according to claim 13, wherein 0≤z<0.4.

### Claim 16 (depends on 11)

The semiconductor device according to claim 11, wherein the first epitaxial layer further comprises Ga in an amount of 5.0×1019 atom/cm3 to 1.0×1021 atoms/cm3.

### Claim 17

A semiconductor device including a FinFET, the FinFET comprising:
three or more fin structures disposed over a substrate such that upper portions of the three or more fin structures protruding from an isolation insulating layer;
a gate structure disposed over parts of the three or more fin structures;
a first epitaxial layer disposed over a source/drain region of each of the three or more fin structures, the first epitaxial layer of one fin structure being separated from the first epitaxial layer of an adjacent fin structure;
a second epitaxial layer disposed over the first epitaxial layer, the second epitaxial layer having a material composition different from the first epitaxial layer;
a third epitaxial layer disposed over the second epitaxial layer, the third epitaxial layer having a material composition different from the second epitaxial layer; and
an electrically conductive contact layer disposed in contact with the first, second and third epitaxial layers, wherein:
the electrically conductive contact layer is in contact with an upper surface and side surfaces of an upper portion of the first epitaxial layer of each of the three or more fin structures,
the first epitaxial layer comprises Si1-xGex, the second epitaxial layer comprises Si1-yGey, and the third epitaxial layer comprises Si1-zGez, where x<y and z<y, and
the third epitaxial layer further comprises at least one of B and Ga in an amount of 5.0×1019 atoms/cm3 to 1.0×1021 atoms/cm3.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein 0≤z<0.4.

### Claim 19 (depends on 18)

The semiconductor device according to claim 18, wherein:
the first epitaxial layers comprise Si1-xGex, where 0.01<x<0.4, and
the second epitaxial layer comprises Si1-yGey, where 0.2<y<0.8.

### Claim 20 (depends on 17)

The semiconductor device of claim 17, wherein the electrically conductive contact layer includes a silicide layer, a glue layer and a body metal layer.