# US 11,309,417 B2 · Method of manufacturing a semiconductor device and a semiconductor device

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- Number: US 11,309,417 B2
- Document ID: US11309417B2
- Status: Granted
- Kind: B2
- Application number: 16/370,668
- Filed: 2019-03-29
- Published: 2019-10-31
- Granted: 2022-04-19
- Earliest claimed: 2018-04-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Blandine Duriez; Mark van Dal; Martin Christopher Holland; Gerben Doornbos
- Web page: https://patentgrep.com/patent/US11309417B2

## CPC

- H10D 30/62: Fin field-effect transistors [FinFET]
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/01: Manufacture or treatment
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10P 14/6506: {Formation of intermediate materials}
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10P 95/906: {for altering the shape of semiconductors, e.g. smoothing the surface}
- H10W 20/032: {of conductive barrier, adhesion or liner layers}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10P 14/24: using chemical vapour deposition [CVD]
- H10P 14/271: {characterised by the preparation of substrate for selective deposition}
- H10P 14/3211: {Silicon, silicon germanium or germanium}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3442: {N-type}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

In a method of manufacturing a semiconductor device, an opening is formed in an interlayer dielectric layer such that a source/drain region is exposed in the opening. A first semiconductor layer is formed to fully cover the exposed source/drain region within the opening. A heating process is performed to make an upper surface of the first semiconductor layer substantially flat. A conductive contact layer is formed over the first semiconductor layer.

## Claims

### Claim 1

A semiconductor device, comprising:
a semiconductor fin structure disposed over a substrate and having a channel region and a source/drain region;
an isolation insulating layer, wherein the channel region and the source/drain region of the semiconductor fin structure protrude from the isolation insulating layer;
a gate structure disposed over the channel region;
a first epitaxial semiconductor layer covering side faces and a top face of the source/drain region;
a conductive contact disposed over the first epitaxial semiconductor layer; and
a dielectric layer disposed over the isolation insulating layer and having an opening, wherein:
the first epitaxial layer is disposed in a lower portion of the opening and the conductive contact is disposed in an upper portion of the opening and is entirely separated from the isolation insulating layer by the first epitaxial layer, and
a variation of a height of an upper surface of the first epitaxial semiconductor layer measured from an upper surface of the isolation insulating layer in the opening is more than 0 nm and less than or equal to 5 nm.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising a second semiconductor layer disposed in the opening between the first epitaxial semiconductor layer and the conductive contact and between the dielectric layer and the conductive contact,
wherein the second semiconductor layer is separated from the isolation insulating layer by the first epitaxial layer.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the first epitaxial semiconductor layer is Ge or Si1-xGex, where 0.3<x<1.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein the first epitaxial semiconductor layer is doped with phosphorous in an amount of 1×1019 atoms/cm3 to 1×1020 atoms/cm3.

### Claim 5 (depends on 3)

The semiconductor device of claim 3, wherein:
the second semiconductor layer is Si or Si1-yGey, where 0<y<0.3.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the second semiconductor layer is amorphous or polycrystalline.

### Claim 7 (depends on 5)

The semiconductor device of claim 5, wherein the second semiconductor layer is doped with phosphorous in an amount of 1×1020 atoms/cm3 to 1×1021 atoms/cm3.

### Claim 8 (depends on 3)

The semiconductor device of claim 3, wherein the first epitaxial semiconductor layer is doped with boron in an amount of 1×1019 atoms/cm3 to 1×1020 atoms/cm3.

### Claim 9 (depends on 3)

The semiconductor device of claim 3, wherein the first epitaxial semiconductor layer is doped with gallium in an amount of 1×1019 atoms/cm3 to 1×1020 atoms/cm3.

### Claim 10 (depends on 3)

The semiconductor device of claim 3, wherein:
the source/drain region is Ge or Si1-zGez, where 0.3<z<1.

### Claim 11 (depends on 1)

The semiconductor device of claim 1, wherein no void is formed at a bottom or sides of the first epitaxial semiconductor layer.

### Claim 12 (depends on 1)

The semiconductor device of claim 1, wherein side faces of the first epitaxial semiconductor layer and side faces of the conductive contact are in contact with an inner wall of the dielectric layer forming the opening.

### Claim 13 (depends on 1)

The semiconductor device of claim 1, wherein the source/drain region and the substrate are made of a same semiconductor material.

### Claim 14 (depends on 1)

The semiconductor device of claim 1, wherein the variation is more than or equal to 0.2 nm.

### Claim 15

A semiconductor device, comprising:
a first semiconductor fin structure and a second semiconductor fin structure arranges side-by-side over a substrate, wherein the first semiconductor fin structure has a first channel region and a first source/drain region and the second semiconductor fin structure has a second channel region and a second source/drain region;
an isolation insulating layer, wherein the first channel region and the first source/drain region of the first semiconductor fin structure and the second channel region and the second source/drain region of the second semiconductor fin structure protrude from the isolation insulating layer, and bottom parts of the first semiconductor fin structure and the second semiconductor fin structure are embedded in the isolation insulating layer;
a gate structure disposed over at least one of the first channel region and the second channel region;
a first semiconductor layer covering side faces and a top face of the first source/drain region and side faces and a top face of the second source/drain region;
a second semiconductor layer disposed on the first semiconductor layer, wherein a material of the second semiconductor layer is different from a material of the first semiconductor layer;
a conductive contact disposed over the second semiconductor layer; and
a dielectric layer disposed over the isolation insulating layer and having an opening, wherein:
a lower portion of the opening is filled by the first semiconductor layer and an upper portion of the opening is filled by the second semiconductor layer and the conductive contact, and
the second semiconductor layer is entirely separated from the isolation insulating layer by the first epitaxial layer.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein a variation of a height of an upper surface of the first semiconductor layer measured from an upper surface of the isolation insulating layer in the opening is more than 0 nm and less than or equal to 5.0 nm.

### Claim 17 (depends on 15)

The semiconductor device of claim 15, wherein a variation of a height of an upper surface of the first semiconductor layer measured from an upper surface of the isolation insulating layer in the opening is more than 0 nm and less than or equal to 3.0 nm.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein the variation is more than or equal to 0.2 nm.

### Claim 19 (depends on 15)

The semiconductor device of claim 15, wherein no void is formed between the first source/drain region and the second source/drain region.

### Claim 20

A semiconductor device, comprising:
semiconductor fin structures arranges side-by-side over a substrate, each of the semiconductor fin structures having a channel region and a source/drain region;
an isolation insulating layer, wherein the channel region and the source/drain region of each of the semiconductor fin structures protrude from the isolation insulating layer and bottom parts of the semiconductor fin structures are embedded in the isolation insulating layer;
a gate structure disposed over at least one channel region of each of the semiconductor fin structures;
a first semiconductor layer covering side faces and a top face of the source/drain region of each of the semiconductor fin structures;
a second semiconductor layer disposed on the first semiconductor layer, wherein a material of the second semiconductor layer is different from a material of the first semiconductor layer;
a conductive contact disposed over the second semiconductor layer; and
a dielectric layer disposed over the isolation insulating layer and having an opening, wherein:
a lower portion of the opening is filled by the first semiconductor layer and an upper portion of the opening is filled by the second semiconductor layer and the conductive contact,
a variation of a height of an upper surface of the first semiconductor layer measured from an upper surface of the isolation insulating layer is 0.3 nm or more and equal to or less than 5.0 nm, and
the second semiconductor layer is entirely separated from the isolation insulating layer by the first epitaxial layer.